Home > Community > Forums > Digital Implementation > Controlling logic names of CTS inserted buffers.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Controlling logic names of CTS inserted buffers. 

Last post Wed, Feb 7 2007 2:08 PM by archive. 5 replies.
Started by archive 07 Feb 2007 02:08 PM. Topic has 5 replies and 1930 views
Page 1 of 1 (7 items)
Sort Posts:
  • Wed, Feb 7 2007 2:08 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Controlling logic names of CTS inserted buffers. Reply

    Hello,
    I was wondering if there is a way to tailor the instance names of buffers inserted by CTS?  Specifically, what I am trying to do is control where in the logic hierarchy the clock buffers are placed.  I would like any buffers inserted by Encounter to be logically placed inside a specific module in the hierarchy.  This allows for easier import back into the Cadence DFII world after Encounter place and route step.

    Anyone had any sucess with this?


    Originally posted in cdnusers.org by nph
    • Post Points: 0
  • Wed, Feb 7 2007 6:58 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    Hi nph,

    No, there is not a way to alter the CTS naming convention to in an effort to influence where in the logical hierarchy clock buffers get inserted. There probably is a way to do what you're asking about via other mechanisms...

    It sounds like your intent here is controlling the physical and logical hierarchy where clock buffers are inserted. Have you noticed that in some cases, CTS will automatically insert buffers within lower levels of hierarchy? It depends on the netlist and partition structure that CTS is faced with.

    I assume your design has partitions that you'd like to see clock buffers inserted within. You may want to have a look at the "pushdownBuffer" command. This command takes buffers that reside over partitions and pushes them down into the partition- taking care of the netlist and physical changes needed to make this happen.

    It would be helpful to understand more about your design challenge here. Specifically: What is the fanout of the clock trees you're building? Like 5 or 30,000? How many partitions in your design?

    Hope this helps,
    Bob


    Originally posted in cdnusers.org by BobD
    • Post Points: 0
  • Thu, Feb 8 2007 8:41 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    Thanks Bob,
    A little more info on what I want to accomplish.
    I'm bringing in a top level Verilog netlist of the design.  This file contains a "digital" module and instatiations for all the pad cells at the top level.  I would like to specify my "AutoCTSRootPin" at the pin clock of the pad cell that is logically in the top level.  However when I do this, Encounter places clock buffers in the top level hierarchy.  I would like to have these buffers placed logically in the "digital" module. 
    So from your post I think I need to create a partition of the "digital" module and use the pushBufferdown command to move any buffers inserted in the top level into the "digital" partition.?.

    However when I try to define the partition from the command line, and gui I get the following message.
    "**WARN: (SOCPTN-406):   Ignoring partition dig_top: Cannot create a partition without any constraint."
    Here is the command I am using.

    definePartition -hinst digital -coreSpacing 1 1 1 1 -railWidth 1 -minPitchLeft 2 -minPitchRight 2 -minPitchTop 2 -minPitchBottom 2 -reservedLayer { 1 2 3} -pinLayerTop { 2} -pinLayerLeft { 3} -pinLayerBottom { 2} -pinLayerRight { 3} -placementHalo 1 1 1 1 -routingHalo 1 -routingHaloTopLayer 3 -routingHaloBottomLayer 1

    Any thoughts?


    Originally posted in cdnusers.org by nph
    • Post Points: 0
  • Thu, Feb 8 2007 12:22 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    The error message you're seeing ("Cannot create a partition without any constraint") is trying to tell us that in order to define a hierarchical module as a partition, you must first define a *placement* constraint for the module within the design. A placement constraint is a guide, region, or fence- in the case of a partition it should be a fence. You can use "createFence" to do this, or via the GUI by dragging the pink module guide from the left of the design into the core area and then calling "definePartition" (or Partition->Specify Partition... via the GUI).

    One other thing comes to mind based on your additional problem description (thanks for that- it's very helpful) is that you might want to try defining your AutoCTSRootPin on the output of an instance within the digital block instead of on the output of a top-level IO. If there is not an instance within the digital block that makes this approach possible, you could add a new buffer for this purpose (using Encounter ECO commands). If you do this, it's possible that the buffers would reside within the partition without any additional effort on your part.

    Feel free to post back for more clarification if you'd like.

    Thanks,
    Bob



    Originally posted in cdnusers.org by BobD
    • Post Points: 0
  • Thu, Feb 8 2007 4:02 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    If you have "fence" for your digital module, then, you may be able to try to turn the "Force CTS to enter only once into fence" in the clock Mode Setup form (it will pop-up if you click "Clock->Set CTS Mode..." Tongju


    Originally posted in cdnusers.org by tzhou@micron.com
    • Post Points: 0
  • Fri, Feb 9 2007 2:06 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    Thanks for all the help!
    I am now able to allow Encounter to insert buffers into the top level of my design and have them inserted logically into a module I specify.  Although it's not the "cleanest" method it works.  This method works buffering clock pins at the top level, and also general purpose pins that drive out of a module, and still allows the buffers to logically be inserted in the specified module.

    Here is the flow I'm using, feel free to make recomendations for improvements...

    Before CTS I use the following commands.

    ###Fence constraint created for module I want all inserted buffers to be placed in.
    createFence 0 0 100000 100000

    ###CTS option to instruct CTS to not create extra ports for any fences defined.  This allows for ###specifying a clock pin as "AutoCTSRootPin" and not have CTS create an extra port.
    setCTSMode -fence

    ###Create partition of module in order to logically put inserted buffers into module given.
    definePartition -hinst

    ###Any buffers residing in partition that have been inserted logically into a different ###module are "pushed" into module specified.  UseExistingPort will attempt not create new ###ports.
    pushdownBuffer -ptn -useExistingPort true


    I had to use the "CTSMode -fence" because giving "AutoCTSRootPin" a clock pin in the top level was causing CTS to create new ports into the "digital" module, which was undesired. 
    I also had to add a "refinePlace" command after CTS in order to fix some cell overlaps that occur between buffers inserted by CTS and regular standard cells.  Not entirely sure why CTS is not fixing these overlaps.?..

    Thanks again for your help.




    Originally posted in cdnusers.org by nph
    • Post Points: 0
  • Fri, Feb 9 2007 2:09 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Controlling logic names of CTS inserted buffers. Reply

    Posted By nph on 2/09/2007 2:06 PM
    Thanks for all the help!
    I am now able to allow Encounter to insert buffers into the top level of my design and have them inserted logically into a module I specify.  Although it's not the "cleanest" method it works.  This method works buffering clock pins at the top level, and also general purpose pins that drive out of a module, and still allows the buffers to logically be inserted in the specified module.

    Here is the flow I'm using, feel free to make recomendations for improvements...

    Before CTS I use the following commands.

    ###Fence constraint created for module I want all inserted buffers to be placed in.
    createFence "module_name" 0 0 100000 100000

    ###CTS option to instruct CTS to not create extra ports for any fences defined.  This allows for ###specifying a clock pin as "AutoCTSRootPin" and not have CTS create an extra port.
    setCTSMode -fence

    ###Create partition of module in order to logically put inserted buffers into module given.
    definePartition -hinst "module_name"

    ###Any buffers residing in partition that have been inserted logically into a different ###module are "pushed" into module specified.  UseExistingPort will attempt not create new ###ports.
    pushdownBuffer -ptn "module_name" -useExistingPort true


    I had to use the "CTSMode -fence" because giving "AutoCTSRootPin" a clock pin in the top level was causing CTS to create new ports into the "digital" module, which was undesired. 
    I also had to add a "refinePlace" command after CTS in order to fix some cell overlaps that occur between buffers inserted by CTS and regular standard cells.  Not entirely sure why CTS is not fixing these overlaps.?..

    Thanks again for your help.





    Originally posted in cdnusers.org by nph
    • Post Points: 0
Page 1 of 1 (7 items)
Sort Posts:
Started by archive at 07 Feb 2007 02:08 PM. Topic has 5 replies.