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 HDL to Layout 

Last post Thu, Jul 16 2009 2:43 PM by mariek. 1 replies.
Started by Dennis Chau 09 Jun 2009 02:37 AM. Topic has 1 replies and 847 views
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  • Tue, Jun 9 2009 2:37 AM

    HDL to Layout Reply

    Hi all,

    What I am looking for is: starting from a design in HDL (VHDL/Verilog using Xilinx), is there any way to translate directly to layout (using Virtuoso LX )

    Would greatly appreciate if anyone can share your experience or point me to relevant documents ?

    Thanks indeed

     

    • Post Points: 20
  • Thu, Jul 16 2009 2:43 PM

    • mariek
    • Not Ranked
    • Joined on Fri, Feb 6 2009
    • Posts 5
    • Points 70
    Re: HDL to Layout Reply

    Hi Dennis,

    Translation from HDL to layout requires logic synthesis to map to from C, behavioral or RTL constructs to a target technology library. Digital physical implementation is then used to map a gate-level netlist to layout using optimizations for area, timing, and power. For synthesis, you may find this reference useful: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=012009_c-to-silicon

    Given your reference to Xilinx: http://www.xilinx.com/tools/designtools.htm

    Best regards,

    Marie

    • Post Points: 5
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Started by Dennis Chau at 09 Jun 2009 02:37 AM. Topic has 1 replies.