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 Analog Layout: interdigitization 

Last post Thu, May 14 2009 10:52 AM by Austin CAD Guy. 4 replies.
Started by luca magnelli 12 May 2009 07:36 AM. Topic has 4 replies and 3582 views
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  • Tue, May 12 2009 7:36 AM

    • luca magnelli
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    • Joined on Thu, Nov 6 2008
    • Arcavacata di Rende, Cosenza
    • Posts 4
    • Points 65
    Analog Layout: interdigitization Reply

    Hi,

    I'm approaching to analog layout with Virtuoso XL. I have to realize the layout of a simple current mirror (2 transistors) and, for matching purposes, I'd like to realize it using an inter-digitized (or common centroid) arrangements.

    There is a way, in Virtuoso XL, to merge 2 or more instances in order to form an inter-digitated one? It seems to me that, starting from a schematic entry and generating the layout from this source, Virtuoso XL only gives separate instances and the only thing to do is routing them.

    Can anyone show me the procedure for activating transistors inter-digitization in Virtuoso XL?

    Thanks,

    Luca

    Luca Magnelli http://www.researcherid.com/rid/A-4363-2009
    • Post Points: 20
  • Tue, May 12 2009 8:54 AM

    • craigth
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    • Joined on Thu, Aug 21 2008
    • Austin, TX
    • Posts 13
    • Points 365
    Re: Analog Layout: interdigitization Reply
    Luca, You didn’t state which IC release and database that your using. The solution recommendations will be different between IC 5141 VXL and IC61 VLS XL.   If you are using IC61 VLS XL then there are several ways you can accomplish this task.   First, you can define constraints using either the Circuit Prospector Assistant which will locate occurrences of structures and devices (e.g. current mirror) on the schematic and automatically apply the appropriate constraints. Or you can manually apply the constraints to the structures and devices using the Constraint Manager Assistant. Using the constraints assigned (e.g. Matched Parameters, Symmetry, Module Generator, etc.) You can find both of these documented in the IC613 Virtuoso Unified Custom Constraint User Guide.  There is also a constraint and feature available in VLS GXL called Module Generators or Modgens. Module Generators are designed to provide a way to generate multiple PCell instances into a complex, highly matched and structured array. Modgens are documented in the IC 613 Virtuoso Analog Placement User Guide. 

    If you need assistance I suggest that you contact Cadence Customer Support and/or your local Field Application Engineer.

    Craig Thompson Sr. Technical Leader Technical Field Operations, North America-Central Region 866.225.3138
    • Post Points: 20
  • Tue, May 12 2009 9:07 AM

    • luca magnelli
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    • Joined on Thu, Nov 6 2008
    • Arcavacata di Rende, Cosenza
    • Posts 4
    • Points 65
    Re: Analog Layout: interdigitization Reply

     Unfortunately I'm using IC 5.1.41, can you suggest me a similar procedure for this release?

    Thanks.

    Luca

    Luca Magnelli http://www.researcherid.com/rid/A-4363-2009
    • Post Points: 20
  • Tue, May 12 2009 9:27 PM

    • craigth
    • Not Ranked
    • Joined on Thu, Aug 21 2008
    • Austin, TX
    • Posts 13
    • Points 365
    Re: Analog Layout: interdigitization Reply

    Luca,

    You maybe able to use the constraints in a similar way using the Group and/or Symmetry constraints available in VXL to achieve what you want. Reference the IC 5141 Virtuoso Constraint Manager User Guide.

    Unfortunately Modgens were not implemented in IC5141 VXL. They were found in the NeoCell product.  The majority of the NeoCell 3.4 features including Modgens, Analog Placer, Cell Planner and Constraints/Constraint Manager were integrated into IC61.

    Craig Thompson Sr. Technical Leader Technical Field Operations, North America-Central Region 866.225.3138
    • Post Points: 20
  • Thu, May 14 2009 10:52 AM

    Re: Analog Layout: interdigitization Reply

    An automatic interdigitation algorithm is pretty complex unless you use the natural capabilities of abutment in aligningthe cells. Using dbMoveFig or rodAlign on a cell does not trigger abutment during a SKILL program but if you follow the move/align command immediately with hiUpdate(), the abutment/spacing will automatially trigger. Thus, you are spared some of the messy calculations for the pcell parameters as the tool will automatically send the abutment program the correct values. Of course, your abutment program has to be working correctly.

    I do not have the algorithm I used before Cadence bought NeoLinear as it was hard to maintain and NeoCell's capabilities were better (in IC6.1 especially).

     Ted

    • Post Points: 5
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Started by luca magnelli at 12 May 2009 07:36 AM. Topic has 4 replies.