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 Bottom-Top design using Concept HDL.. 

Last post Thu, Jan 10 2013 6:10 AM by admin. 8 replies.
Started by MAAC 04 May 2009 10:09 PM. Topic has 8 replies and 4460 views
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  • Mon, May 4 2009 10:09 PM

    • MAAC
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Bangalore, Karnataka
    • Posts 195
    • Points 3,620
    Bottom-Top design using Concept HDL.. Reply

    Hi,

    I would like to know the Bottom-Top design approach in HLD...or hierarchical design from Bottom to top..???

    Which is prefered one Top-Bottom or Bottom-Top??...I could able to do the Top-Bottom design using Concepthdl_tut.pdf from Doc....

    How can we do the Bottom-Top design r is there any user guide for the same.(not the Tools-Genview)

     

    Thnx

    • Post Points: 35
  • Tue, May 5 2009 2:26 PM

    Re: Bottom-Top design using Concept HDL.. Reply

     Hi MAAC,

    I typically do bottom>top work. Here is the procedure that I use:

     1. Create a new project. Open the schematic (you'll be at the 'root' page) and go to File > New. This will be your hierarchical block schematic.

    2. Once you're composed the circuitry for the block, leave the nets that go to the ports (pins of the block) dangling.

     3. Go to File Save As to save this schematic page as a Cell. In addition to naming the cell, make sure the View is Schematic. Accept the errors/warnings when saving.

    4.  Add ports to the design and name those nets that leave and hierarchical block. Save again.

    5.  Go to Tools > Generate View. I accept the default settings, click Generate then Done, and close the schematic page. You're now back at the 'root' schematic page.

    6. Using the Component Browser, you can add the hierarchical block from the project's root library like any other component.

    7. Once placed, you can manipulate the block by pulling it up with File > Open. The changes will automatically propogate to the 'root' level.

     

    Is that what you're looking for?

    • Post Points: 20
  • Wed, May 6 2009 4:05 AM

    • MAAC
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Bangalore, Karnataka
    • Posts 195
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    Re: Bottom-Top design using Concept HDL.. Reply

    Thnx Evan,

    ....:):)

    • Post Points: 20
  • Tue, Feb 22 2011 6:53 PM

    Re: Bottom-Top design using Concept HDL.. Reply

    How to deal with power pins for the reuse blocks? When I add an outport with the signal name "+5V_USB" to the block, an error appears: Schematic has port but port does not exist in the symbol. Either delete this port from the schematic or add this port in the symbol.

    Does it mean I can't add power port to reuse blocks?

    • Post Points: 20
  • Wed, Feb 23 2011 5:10 AM

    • Jerry GenPart
    • Top 75 Contributor
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    • Lake In The Hills, IL
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    RE: Bottom-Top design using Concept HDL.. Reply
    This error usually means that since you added an OUTPUT symbol with the signal name "+5V_USB", it needs to see this same logical pin name on the hierarchical block that represents this logical schematic. If you don’t need to bring the "+5V_USB" signal to the hierarchical block symbol, then just remove the OUTPUT symbol attached to the "+5V_USB" signal/wire.

    Jerry
    Regards,

    Jerry
    • Post Points: 20
  • Wed, Feb 23 2011 6:48 PM

    Re: RE: Bottom-Top design using Concept HDL.. Reply
    Hi Jerry, Thank you so much for your response.

    This error also appears when I modify a reuse module. I want to modify a reuse module that has already been placed into a board layout. When I modify the subdesign schematic and save it, errors appear: ERROR(SPCOHD-168):Schematic has port but port does not exist in the symbol. Either delete this port from the schematic or add this port in the symbol.Then I cannot package the subdesign schematic. I just changed some signal names of the subdesigns. I don't know why these errors exsit even I delete all the modules in the top-level schematic.
    Could you please help me to solve it?

    Thanks.
    Best Regards,
    Samuel

     

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    • Post Points: 20
  • Thu, Feb 24 2011 7:21 AM

    • Jerry GenPart
    • Top 75 Contributor
    • Joined on Tue, Jun 17 2008
    • Lake In The Hills, IL
    • Posts 128
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    RE: RE: Bottom-Top design using Concept HDL.. Reply
    Make sure that whenever you change the lower level hierarchical block’s signal names that are attached to PORT symbols, that you also insure you either run Genview (to update the corresponding block symbol) or manually modify/add/delete the same signal’s pin name in the block’s symbol view.

    Save both the block schematic and the corresponding symbol view.

     

    Jerry
    Regards,

    Jerry
    • Post Points: 20
  • Thu, Feb 24 2011 9:58 PM

    Re: RE: RE: Bottom-Top design using Concept HDL.. Reply

    Hi Jerry. Thank you for your reminding. I already solved this problem. The matter is that I must make 'Generate view' at first before I saving the subdesign which I modify. If I save the subdesign immediately after modifying, the errors will appear.

    Thanks

    • Post Points: 5
  • Thu, Jan 10 2013 6:10 AM

    • admin
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    • San Jose, CA
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    ERROR(SPCOHD-152) Reply

     Hi,

    What is this error and how it can be resolved.

     

    Severity : Error (HDL Direct)
    Description : ERROR(SPCOHD-152): Port on instance does not exist in entity declaration for instance.
    Object dump:
    {
        page:  1
        instance:  I115
        cell name: STM32F103VGT6
        pin name:  PB11/I2C2_SDA/USART3_RX
    }
    {
        page:  1
        instance:  I115
        cell name: STM32F103VGT6
    }

    • Post Points: 5
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Started by MAAC at 04 May 2009 10:09 PM. Topic has 8 replies.