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 SOC timing problem 

Last post Fri, Sep 8 2006 9:07 AM by archive. 8 replies.
Started by archive 08 Sep 2006 09:07 AM. Topic has 8 replies and 3342 views
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  • Fri, Sep 8 2006 9:07 AM

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    SOC timing problem Reply

    Hi all,


    I've a post-P&R timing problem using SOC Encounter.
    As you can see in the attached file,
    my circuit generates an inverted clock.


     
    The timing analyzer reports a setup-violation between
    two FFs which use the inverted and the positive clock.
     
    I've read the reports and I've found that
    the combinational delay  MAX_DELAY is less than the clock  period.
    The problem is that the analyzer doesn't identify the correct clock edges
    for setup checking.
    In particular it should consider the next edge
    of  CLK_END for a correct check.



    In order to eliminate the false violation, I've tried to declare
    CLK_NEG as a generated clock in the sdc constraint file:

    create_generated_clock  -name CLK_NEG -source CLK -invert [get_pins "MODULE_PATH"/MYMOD/INV/Z]

    But I get the folloving warning messages:

     >Skipped invalid point "MODULE_PATH"/MYMOD/INV/Z
     >Empty pin list in get_pins command
     >Unsupported commad  "create_generated_clock"
     
     
     I've the following questions:
     
     1. The "create_generated_command" could actually avoid the false violation?
     
     2. If So, can it be applied in a hierarchycal module?
     
     3) What is the correct syntax?
     
     
     Sorry for the long post,
     thank you.


    Originally posted in cdnusers.org by giohdl
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  • Sun, Sep 10 2006 7:00 PM

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    RE: SOC timing problem Reply

    Hello Friend !!

    A1. Yes
    A2. YES
    A3. a sample for your ready reference
    create_generated_clock -name CLK_NEG -source [get_pins \
    {SYSX/SYSY/friend/CLKROOT/A} \
    -divide_by 1 -invert -add -master_clock [get_clocks {CLK}] [get_pins \
    {SYSX/SYSY/friend/CLKROOT/Z}


    some use-full information about "create_generated_clock" options.
    +---+---+---+---+---+-------------------------+
    |BG |FE |CTE|RC |CCD| SYNOPSYS |
    +---+---+---+---+---+-------------------------+
    | Y | Y | Y | Y | Y | create_generated_clock
    | Y | Y | Y | Y | Y | [-name clock_name]
    | Y | Y | Y | Y | Y | -source master_port_pin
    | Y | Y | Y | Y | Y | [-divide_by factor |
    | Y | Y | Y | Y | Y | -multiply_by factor]
    | Y | Y | Y | Y | Y | [-duty_cycle percent]
    | Y | Y | Y | Y | Y | [-invert]
    | Y*| Y*| Y*| Y*| Y | [-edges edge_list]
    | Y*| Y*| Y*| Y*| Y | [-edge_shift shift_list]
    | Y | Y | Y | Y | Y | [-add] (SDC 1.4)
    | Y | Y | Y | Y | Y | [-master_clock clock] (SDC 1.4)
    | - | - | - | Y | - | [-domain domain_name] (Non-SDC, Non-Synopsys)
    | - | - | - | Y | - | [-mode mode_name] (Non-SDC, Non-Synopsys)
    |---|---|---|---|---| object_list :
    | Y | - | Y?| Y | Y | hierarchical pins
    | Y | - | Y | Y | Y | ports
    | Y | Y | Y | Y | Y | pins
    +---+---+---+---+---+-------------------------+
    * FE/BG/RC/CTE UNSUPPORTED :number of edge > 3

    NOTE :
    =========================================
    Key
    =========================================
    Y : Supported
    - : Not supported
    ? : Unclear, requesting R+D feedback
    / : Not applicable (FE-CTE is timing analysis only)

    =========================================
    Software Version Info
    =========================================
    BG : 5.0.14 Ambit BuildGates
    FE : 05.20-e093_1 First Encounter (FE-STA)
    CTE : 05.20-e093_1 CTE in FE
    RC : 05.20-s012_1 RTL-Compiler
    CCD : 1.0 USR1 Conformal Constraint Designer
    SYNOPSYS : SDC 1.5 Synopsys PT/DC


    With Regards,
    Mohan Kumar Ch


    Originally posted in cdnusers.org by mohanch007
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  • Sun, Sep 10 2006 7:46 PM

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    RE: SOC timing problem Reply

    oops let me correct the syntax

    create_generated_clock -name CLK_NEG -source [get_pins \
    {SYSX/SYSY/friend/CLKROOT/A}] \
    -divide_by 1 -invert -add -master_clock [get_clocks {CLK}] [get_pins \
    {SYSX/SYSY/friend/CLKROOT/Z}]

    thanks


    Originally posted in cdnusers.org by mohanch007
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  • Sun, Sep 10 2006 9:01 PM

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    RE: SOC timing problem Reply

    Hi giohdl,

    While what you are doing can work, I think which edge the tool will use depend on how you define the clock in the first place. The tool will always use the "ideal" clock (i.e. the clock you defined) to determine the clock edge.

    It will be clearer for us if you show us how the clocks are defined.

    In this case, I think re-define the clocks source might work better (in the sense that it is closer to the specification). If the clock source is okay, then I think this path is then a multi-cycle path (becareful. You are capturing a value when it is not stable; potential meta-stable problem here).

    Also, note that "set_max_delay" take into the consideration of clock skew; this is the defination in the SDC.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Mon, Sep 11 2006 6:39 AM

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    RE: SOC timing problem Reply

    Hi,
    first I must admit my poor practice in constraining designs.
    I've just declared the ideal clock signal this way:

    create_clock [-get_pins {pad_clock/Z}] -name ideal_CLK -period 2 -waveform{0 1}


    As you suggested, I've used the "create_generated_clock" constraint
    and repeated the timing analysis on my layout.
    The timing analyzer now considers CLK_NEG as a clock and doesn't report
    the previous setup violations.

    Actually I think that  layout design
    must repeated and include proper constraints for the generated clock signals.
    I've read the CTS reports and I've seen that
    clocktree generation has been ignored for all FFs driven by CLK_NEG.
    As a result there is a big latency (unbalanced phase delay) for those paths.

    I've attached the real timing.
    CLK and CLK_NEG have a latency of about 1ns respect to the ideal clock.
    CLK_END has a latency of about 300ps.

    I suppose that it's necessary to include the  generated clock
    requirements in the clocktree generation tool.
    Beside the sdc file,
    could you tell me how to modify the CTS constraint file?

    Thank you again.
    Regards,
    Giohdl


    Originally posted in cdnusers.org by giohdl
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  • Mon, Sep 11 2006 6:22 PM

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    RE: SOC timing problem Reply

    Dear Giohdl,
    Delighted seeing your explanation.
    In general in system mode all the critical paths are synchronous in nature (only rising edge-triggered )
    Aside please let me add my comments on CTS constraints file. (design.ctstch)
    Things to be considered
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    2. Ideal CLK MaxDelay (setup) and MinDelay (hold) (set_clock_latency).
    3. handling generated clock in CTS by hierarchically CTS ( preserve pin)
    4. Skew alignment for Rising Sync Pins and Falling Sync Pins

    Out of the above 4 topics I will help you in 1 and 3 which are the two different approaches.
    1. Skew alignment (MaxSkew) between clock groups (CLK,CLK_NEG,CLK_END).
    ClkGroup
    + clockRootPinName
    + clockRootPinName
    You can use the ClkGroup section to balance clock skew between two or more clock trees.

    Alternatively, you can balance skew as follows:
      * run CTS once
     * specify MinDelay constraints for all clock trees with the largest clock phase delay, and
     * rerun CTS. However, using ClkGroup often provides better results.
     It is recommended to use ClkGroup with MinDelay 0 if you need to balance clock skew among multiple clock trees.

    • Clock Tree Specification File Example

    ##------- RouteType
    RouteTypeName double_space
    TopPreferredLayer 7
    BottomPreferredLayer 5
    PreferredExtraSpace 1
    NonDefaultRule double_width
    End

    ##------ Clock Group (Balance skew between two clock trees)
    ClkGroup
    + CLKROOT1/Z
    + CLKROOT2/Z
    ##------ CLK1 -------
    AutoCTSRootPin CLKROOT1/Z
    MaxSkew 300ps
    MinDelay 0.000ns
    MaxDelay 10.000ns
    SinkMaxTran 500ps
    BufMaxTran 500ps
    MaxFanout 32
    addDriverCell BFX8
    LeafPin
    PreservePin
    + BLOCK1/MODULE4/CELL4/Z
    End

    • method 2

             Preserves the net-list after the specified pin.
              FE-CTS builds other portions of a clock tree in such a manner as to balance clock skew with
             the  preserved logic.
              See Figure for Ex. of PreservePin


    Originally posted in cdnusers.org by mohanch007
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  • Thu, Jan 18 2007 6:15 PM

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    RE: SOC timing problem Reply

    Hello,

    Have you found a solution to this issue?
    Thanks.

    BC


    Originally posted in cdnusers.org by bridgeport37
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  • Fri, Jan 19 2007 7:36 AM

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    RE: SOC timing problem Reply

    Hello BC,

    I've solved the problem using
    the "ThroughPin" command for the inverter in the CTS file.
    This way I use a single clock.
    Moreover, since the circuit is not big,
    the skew is also acceptable.

    Thanks,
    Giohdl


    Originally posted in cdnusers.org by giohdl
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  • Thu, Apr 19 2007 3:08 AM

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    RE: SOC timing problem Reply

    Hello All,
    Initial question was that why tool is showing the wrong path. I think here there should not be any reuirement of declaring the create_generated_clock.
    Tool should properly show the path. may it is a bug in tool.


    Originally posted in cdnusers.org by anil yadav
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Started by archive at 08 Sep 2006 09:07 AM. Topic has 8 replies.