SVA failures can be a bit confusing like this, especially if you're used to PSL.
In SVA, all assertions are defined as "strong" meaning that they must finish before the end of simulation, else they fail at the end of simulation. In PSL you have a choice of the default "weak" assertion which won't automatically fail at the end, or you can use the "!" operator to force an assertion to be strong.
Another thing you may see (at least, I've nearly tripped over it a couple of times) is that classic thing of looking a the bottom of the screen and reading the first error that you see on the screen. If you see an SVA assertion has failed at the end of the sim, and you think it is a bit weird, then your first reaction needs to be to scroll up through the log to look for some other thing that has terminated the sim.
For example in an OVM testbench, did some class-based check terminate with a dut_error()? If so, you'll see that message much further up the log compared to any final (and spurious) SVA failures...
All good fun, I suppose ;-)