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 How to analyze pin accessibility? 

Last post Mon, Aug 21 2006 9:14 PM by archive. 2 replies.
Started by archive 21 Aug 2006 09:14 PM. Topic has 2 replies and 1264 views
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  • Mon, Aug 21 2006 9:14 PM

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    How to analyze pin accessibility? Reply

    Hello everybody,

    I am starting to work on the second rev of an hard IP and based on the first rev issues I believe I might have some pin accessibility issue on standard cells and some large macros.

    Can anyone share how you find those? Is FE having any capability to analyze LEF models and report pins with bad accessibility either cell by cell or in a placed design.

    Thanks in advance for your help,
    Eric.


    Originally posted in cdnusers.org by evenditti
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  • Mon, Aug 21 2006 9:42 PM

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    RE: How to analyze pin accessibility? Reply

    Hello there !!
    check the below command for pin accessibility issue ,
    The following command checks the floorplan and generates a text version of the report called checkDesign.rpt
    NAME : " checkDesign"
    Examples
    checkDesign -physicalLibrary -noHtml -outfile checkDesign.rpt

    The above command also checks for missing or inconsistent Physical library (LEF) The software
    generates error messages for the following conditions:
    - Cells not defined in LEF
    - Cells with missing dimensions
    - Pins with missing direction
    - Cells pins with missing geometry
    - Cell dimensions are not an integer multiple of the core site dimensions


    referred FE tool version : First Encounter v05.20-s116_1

    -Mohan Ch


    Originally posted in cdnusers.org by mohanch007
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  • Tue, Aug 22 2006 3:11 AM

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    RE: How to analyze pin accessibility? Reply

    Hi Eric,

    For std cell, when I was using a non-cadence flow, pin accessability is done by drawing a metal 1 ring half metal pitch around each std cell, and then try to route from outside the metal1 ring to every pin of the standard cell. I think this can be done about the same way in encounter... just instantiate all types of cells, place them all on one row, and every pins has an IO pin. If the routing fail, then there is accessability problem. No a catch-all solution, but might be useful.

    As for macro, I think the best method is to make all pin double pitch, but this usually result in an unnecessary wide pin. As macro's pins is usually at the boundary, there should be no accessability issue. The main issue I have is the modellign of the OBS in the macro to make the router aware of how far to put a wire or via.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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Started by archive at 21 Aug 2006 09:14 PM. Topic has 2 replies.