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 Stack via on spare gates' pins 

Last post Mon, Aug 14 2006 6:10 PM by archive. 6 replies.
Started by archive 14 Aug 2006 06:10 PM. Topic has 6 replies and 2095 views
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  • Mon, Aug 14 2006 6:10 PM

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    Stack via on spare gates' pins Reply

    Hi layout-ers!

    Need your advise on implementing an requirement for spare gate.

    I need to put some spare gates in the design; I can do this, and place it well.

    However, there is a requirement that the pins of the spare gates (input and output) should have a stacked via on top of its an all the way to the top metal. This is to increase the chance of changing less metal layers when eco is using the spare gates.

    So, I need to

    1. Do not place the spare gate under power stripes (if not the stacked via will short to the power (input pins are connected to tie-high/tie-low)
    2. find a way to add the stacked via on the pins (and even better the gloabl router is able to optimise the routing for congestion with the existance of these stacked via)

    One easier way is to create standard cell with those pins; but unfortantely  the standard cell library I am using does not have these features, and I do not wish to create new cells with the stacked pins...

    Anyone done this before and know the correct way to do this in SOC? Thanks.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Tue, Aug 15 2006 9:00 AM

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    RE: Stack via on spare gates' pins Reply

    Hello Eng Han ,

    Please find if this can help you out .
    In your mail you told that your spare gates are placed well !! ( you mean legalisation of placement ?? )

    In my understanding you have created the placement restrictions for spare cells . ( am i right ?? ) .
    if the spare cells have no placement restriction , they are scattered on the whole design ( row -core area ) , at the time of cell placement.
    When you want to place spare cells in the specific are , give placement restrictions ( to create regions & groups ) .
    for creating group for spare cell use "createInstGroup" cmd.
    to add spare cells to that group created use "addInstToInstGroup" cmd.
    for creating a region for the group use "createRegion"
    (ex. createRegion SPAREGROUP_case1 sx sy lx ly )

    During Place cells ( placement setup for logical cells )
    Specify the layer to treat as placement obstruction area under power routing
    setPrerouteAsObs { layers} .
    as placement engine eastimates timing routing congestion based on trialRoute result use "setTrailRouteMode" options ,
    like min/max RoutingLayers .

    finally before spare cell placement define spare cells by using "specifySpareGate -inst " cmd.
    go ahead with placement .

    for place cell which ware added by ECO use "ecoPlace -useSpareCells " option .

    Hope this will help to some extent .

    good luck !!


    Originally posted in cdnusers.org by mohanch007
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  • Tue, Aug 15 2006 7:17 PM

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    RE: Stack via on spare gates' pins Reply

    Hi Mohan,

    Thanks for the tip. But I think you miss my point.

    The main concern is how to add stack via on top of the pins of the spare gate (and not placing the spare gate).

    I believe that SOC does not have direct command to add stack via on the pins. I can write some code to do this, but I wish to know how other people do this (I have learnt this requirement several years ago, but I personally is doing this the first time) before I spend time in the coding.

    However, I understand that with this requirement, there are added restriction to the placement flow. Firstly, I think the option "setPrerouteAsObs" is too restrictive as it also prevent non-spare-gate to be keep out of power stripes, result is huge loss in untilizaiton. Secondly, the stack via can only be added after placement (infact after cts, and possibility just before detailed route), the global router don't see this and cannot optimise the congestion with these stack via. I hope there is some smarter way to implement the flow.


    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Tue, Aug 15 2006 7:50 PM

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    RE: Stack via on spare gates' pins Reply

    Hi Eng Han,

    I need to highlight the purpose of "setPrerouteAsObs" is only to avoid routing problem  as you have requested in
    > 1. Do not place the spare gate under power stripes (if not the stacked via will short to the power (input pins are > connected to tie-high/tie-low)

    like if you specify Std. cell metal layers like M1,M2,M3 ( metal layers Std cells constructed ) .
    if you don't consider this even through this will result in  loss in utilization you will finally end in VG/VC physical violation.
    > Firstly, I think the option "setPrerouteAsObs" is too restrictive as it also prevent non->spare-gate to be keep out of power stripes, result is huge loss in utilization.


    Regards,
    -Mohan


    Originally posted in cdnusers.org by mohanch007
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  • Wed, Aug 23 2006 2:59 AM

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    RE: Stack via on spare gates' pins Reply

    Hi,

    I will be started to "engineer" a way to put stack via on spare gates' pins tomorrow. If you have experience on this task, I will be grateful if you can share it with me. Thanks!

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Wed, Aug 23 2006 8:03 AM

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    RE: Stack via on spare gates' pins Reply

    what is your experience of using SOCE for metal only eco.  ex. If i have 6 routing layers, M1-M6 and i only want to do M3-M5 metal only eco (i know it can be done by looking at the route).  I just want know the usefullness of this stack vias spare gate.

    Thanks.

    li siang


    Originally posted in cdnusers.org by lisiang
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  • Wed, Aug 23 2006 7:48 PM

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    RE: Stack via on spare gates' pins Reply

    Hi Li Siang,

    I have to admit that I have not done ECO using spare gate before! All my ECO experience has to deal with re-wiring the non-spare cell. I usually prefer to do the eco routing by hand to assure me that minimum changes to the routing, but I am also observed that auto-ECO routing can do a very good job in preserving existing routing.

    Usually 2 routing layers (at metal3 or above) and 1 (or 2) via layers are sufficient for simple eco routing. If spare cell is just tie high/low and output is unconnected, then we will need to change metal 1/via12/metal2/vial23 also, which make the eco costly. So from this aspect, if we have stack via on spare gate, eco with spare gate can make with less metal layers.

    The idea of stack via on spare gate is quite well-known in serveral companies; they have special standard cell that have this stack via build in (a workaround as most P&R tool I know does not support this requirement). However, a few years ago most P&R tools have problem using those cell as the tool "cannot detect that the standard cell short with the power stripes".

    A special version of this stack via requirement is some special FF has a "probe point" to allow for wafer level probing.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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Started by archive at 14 Aug 2006 06:10 PM. Topic has 6 replies.