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 Generating layout and iterating over it 

Last post Fri, Apr 10 2009 8:29 AM by Austin CAD Guy. 1 replies.
Started by gsimard 07 Apr 2009 06:42 AM. Topic has 1 replies and 1097 views
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  • Tue, Apr 7 2009 6:42 AM

    • gsimard
    • Top 500 Contributor
    • Joined on Fri, Mar 20 2009
    • Posts 21
    • Points 465
    Generating layout and iterating over it Reply

    Hello all,


    First of all, sorry for cross-posting this, but I felt this thread might answer this.

    Is there a way to automate an optimization process that would need a post-layout extracted view to get its goals ?

    For example, I have written a PCELL in skill that generates a ring oscillator from transistors. The sizes of these transistors can be specified on the instance of the PCELL in the level 0 layout. Then I need to place pins and labels over the right metal parts to meet my symbol's pins.

    After that, I execute a layout extraction, which is toolkit specific and in my case could be launched from command line.

    I then run a simulation from the analog environment in my test bench schematic which uses the symbol of the oscillator and I use the hierarchy editor to specify that it should use the extracted view for simulation.

    I then calculate the frequency of the oscillator with the calculator (DFT, max).

    The goal would then be that this frequency reach say 5 MHz, so I would like to setup the analog circuit optimization to iterate this procedure.

    Can this be done easily ? If not easily, I am willing to code a bit, but I would need pointers for this one !


    Thank you,
    Guillaume Simard

    • Post Points: 20
  • Fri, Apr 10 2009 8:29 AM

    Re: Generating layout and iterating over it Reply

     Hi Guillaume

    I am trying to understand exactly what you are trying to do so let me paraphrase it:

    You have a ring oscillator pcell (RO) which internally instantiates transistors to create your device. The transistor sizes are parameterized at the RO level so the correct layout is automatically generated by the pcell

    You are using the extracted layout in your simulation.

    Now you want to adjust the pcell parameters to optimize the layout to reach your goal. Repeat these steps till the goal is reached.

    There are two parts which  would need additional information, how you are generating the extracted data and how you are making the decision as to which parameter values to change. You can use VirtousoLS-XL to update the parameters on the layout from the schematic of the RO placement ( assuming IC6.1, otherwise use VXL). Without knowing the tool which is generating the extracted view, I would have to suggest using IPC to start that tool and wait till it is finished. Then start the simulation. Once the simulation is set up to use that view in the hierarchy, it should do so in each iteration.

    The simulation results would have to be analyzed with a program which can decide on which parameters to tweak, this is mapping what we do visually and mindfully into a rule based analyzer, Cadence may have something like that already but that is front end and I'm not an expert there. Check with your local front end AE on that.The interaction of the parameter values could be very complex but since it is a single device, it is not an impossible job to create the rules to drive the changes in SKILL.

    If I could get more details, I could give more suggestions.

     Ted

    • Post Points: 5
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Started by gsimard at 07 Apr 2009 06:42 AM. Topic has 1 replies.