I am trying to understand exactly what you are trying to do so let me paraphrase it:
You have a ring oscillator pcell (RO) which internally instantiates transistors to create your device. The transistor sizes are parameterized at the RO level so the correct layout is automatically generated by the pcell
You are using the extracted layout in your simulation.
Now you want to adjust the pcell parameters to optimize the layout to reach your goal. Repeat these steps till the goal is reached.
There are two parts which would need additional information, how you are generating the extracted data and how you are making the decision as to which parameter values to change. You can use VirtousoLS-XL to update the parameters on the layout from the schematic of the RO placement ( assuming IC6.1, otherwise use VXL). Without knowing the tool which is generating the extracted view, I would have to suggest using IPC to start that tool and wait till it is finished. Then start the simulation. Once the simulation is set up to use that view in the hierarchy, it should do so in each iteration.
The simulation results would have to be analyzed with a program which can decide on which parameters to tweak, this is mapping what we do visually and mindfully into a rule based analyzer, Cadence may have something like that already but that is front end and I'm not an expert there. Check with your local front end AE on that.The interaction of the parameter values could be very complex but since it is a single device, it is not an impossible job to create the rules to drive the changes in SKILL.
If I could get more details, I could give more suggestions.