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 Using the Virtuoso Analog Circuit Optimization to iterate on layout geometries 

Last post Mon, Apr 6 2009 11:17 AM by gsimard. 0 replies.
Started by gsimard 06 Apr 2009 11:17 AM. Topic has 0 replies and 1371 views
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  • Mon, Apr 6 2009 11:17 AM

    • gsimard
    • Top 500 Contributor
    • Joined on Fri, Mar 20 2009
    • Posts 21
    • Points 465
    Using the Virtuoso Analog Circuit Optimization to iterate on layout geometries Reply

    Hello all,


    Is there a way to automate an optimization process that would need a post-layout extracted view to get its goals ?

    For example, if I have written a PCELL in skill that generates a ring oscillator from transistors. The sizes of these transistors and number of inverters can be specified on the instance of the PCELL in the level 0 layout.

    Then I need to place pins and labels over the right metal parts to meet my symbol's pins.

    After that, I execute a layout extraction, which I read is toolkit specific and in my case could be launched from command line.

    I then run a simulation from the analog environment in my test bench schematic which uses the symbol of the oscillator and I use the hierarchy editor to specify that it should use the extracted view for simulation.

    I then calculate the frequency of the oscillator with the calculator (DFT, max).

    The goal would then be that this frequency reach say 5 MHz, so I would like to setup the analog circuit optimization to iterate this procedure.

    Can this be done easily ? If not easily, I am willing to code a bit, but I would need pointers for this one !


    Thank you,

    Guillaume Simard

    • Post Points: 5
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Started by gsimard at 06 Apr 2009 11:17 AM. Topic has 0 replies.