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 verilogA to verilog translation 

Last post Thu, Mar 19 2009 7:21 PM by aplumb. 1 replies.
Started by vlau2 19 Mar 2009 02:45 PM. Topic has 1 replies and 1847 views
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  • Thu, Mar 19 2009 2:45 PM

    • vlau2
    • Not Ranked
    • Joined on Thu, Jul 17 2008
    • Newport Beach, CA
    • Posts 9
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    verilogA to verilog translation Reply

    Is there any utility (official or unofficial, crude or robust) to translate verilogA code to verilog, it doesn’t have to capture all the details but anything that can be translated will be helpful.

    • Post Points: 20
  • Thu, Mar 19 2009 7:21 PM

    • aplumb
    • Top 75 Contributor
    • Joined on Thu, Jul 17 2008
    • Ottawa, Ontario
    • Posts 80
    • Points 1,230
    Re: verilogA to verilog translation Reply
    Verilog-A could be anything from abstract V/I assignment operations to primitive device instantiation and everything in between. It's not going to be a simple translation by any stretch. Can you be more specific about what's being modeled in Verilog-A and how the generated Verilog model is intended to be used?
    • Post Points: 5
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Started by vlau2 at 19 Mar 2009 02:45 PM. Topic has 1 replies.