Hi, Originally posted in cdnusers.org by EngHan
Depend on alot of things ... important one are number of metal layers, and project schedule. Also heavily depend on the ASIC library (e.g. some D0, D1 and D2 have the same size, and thus utilization can be higher).
I think the best reference is the previously tape-out design. I observed that for Encounter, when the design and constraint are not stable, the utilization can increase by more than 10% before and after physical synthesis. At tape-out time where the quality of the design and constraint are good, the utilization increase is smaller. Perhaps this is due to the natural of the design I am working on. Anyway, this make targeting a utilisation difficult.
I think a final utilization of about 80% should be okay for 6 metal process.