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 Questiorn: what should be the starting utilization for a new design 

Last post Wed, May 17 2006 6:14 AM by archive. 2 replies.
Started by archive 17 May 2006 06:14 AM. Topic has 2 replies and 1293 views
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  • Wed, May 17 2006 6:14 AM

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    Questiorn: what should be the starting utilization for a new design Reply

    When starting a new design (chip or hier block), how do one determines the initial utilizattion with and without any hard macro.  Any opion on the ideal util. for SOCE.

    Thanks.

    li siang


    Originally posted in cdnusers.org by lisiang
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  • Mon, May 22 2006 5:29 PM

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    RE: Questiorn: what should be the starting utilization for a new design Reply

    Hello,

    Encounter will give you the utilization for both core area and cell utilization.

    Go to:

    Floorplan -> Specify Floorplan

    Look for "Core" or "Cell Utilization".

    These values are available post design import.

    You can also run:   reportDesignUtil:

    [DEV]encounter 19> reportDesignUtil

    Chip Utilization = 0.668
    Core Utilization = 0.680
    Standard Cell Area Utilization = 0.378

    During floorplan you should target approx. 75% utilization (this is somewhat design
    dependent), but you need to account for optimization and CTS.

    Regards,

    Elvis


    Originally posted in cdnusers.org by elvis
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  • Wed, May 24 2006 5:55 AM

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    RE: Questiorn: what should be the starting utilization for a new design Reply

    Hi,

    Depend on alot of things ... important one are number of metal layers, and project schedule. Also heavily depend on the ASIC library (e.g. some D0, D1 and D2 have the same size, and thus utilization can be higher).

    I think the best reference is the previously tape-out design. I observed that for Encounter, when the design and constraint are not stable, the utilization can increase by more than 10% before and after physical synthesis. At tape-out time where the quality of the design and constraint are good, the utilization increase is smaller. Perhaps this is due to the natural of the design I am working on. Anyway, this make targeting a utilisation difficult.

    I think a final utilization of about 80% should be okay for 6 metal process.

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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Started by archive at 17 May 2006 06:14 AM. Topic has 2 replies.