Hi Mohan,Originally posted in cdnusers.org by EngHan
Perhaps I am not clear.
The jtag cell is not a FF. It is a few combinatorial cells. The cells
that drive the pad are placed close to the pad. That is okay. However,
as I have mentioned, the design has alot of bi-direcitonal pads, and
the timing path through the jtag module consist of a few combinatorial
cell. Some of these combinatorial cell is shared by several pads, so
they cannot be placed near a pad, but in the middle of sevaral pads.
This is fine also.
However, logic synthesis could not know that there is a considerable
distance between the placement of the jtag cells, so it use a small
drive, and not buffering. After placement, some sizing and buffering
will meet the timing relatively easy. The issue is after jtag
placement, the jtag cells are "FIXED", so the tool cannot size it (I am
not sure if the tool can buffer it).
For now, I re-fix it after placeDesign so that optDesign can do
something about it. Still, after optDesign, the tool fix half of them,
but some still have nasty -1.2ns slack. So I have to size all the jtag
cells manually in the netlist before placeDesign. I think there is
something wrong in the flow, so I am asking a better way to do this.