Hi,Originally posted in cdnusers.org by EngHan
Would like to know how the following can be handled in Encounter flow.
The data path is from a FF to another FF, and both FF are clocked by
the same clock. In the data path, there is an OR gate. One of the input
of the OR gate is from a clock source. The other input of the OR gate
As the OR gate is part of a clock network, the placer does not optimise
it. Hence, during optDesign, due to the high-fanout of the OR gate, the
delay of the OR gate is 200+ns. This result in a huge violation, and
the QOR become bad.
I have tried to use "setAnalysisMode noclksrcpath", but since the source of this path is data, the option does not effect.
I workaround by setting a multicycle path from these 2 FFs during
physical synthesis, and then remove it before clock tree synthesis.
However, is there a better solution for this type of design? Thanks.