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  Leakage currents & mismatch 

Last post Thu, Feb 19 2009 11:46 PM by Ling. 1 replies.
Started by mb47 02 Feb 2009 12:09 PM. Topic has 1 replies and 1157 views
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  • Mon, Feb 2 2009 12:09 PM

    • mb47
    • Not Ranked
    • Joined on Thu, Jul 17 2008
    • Posts 3
    • Points 60
    Leakage currents & mismatch Reply

    Hi all, is there a way to simulate the effect of mismatch in parasitics (in particular parasitic diodes)?

    The pn junction of n-wells for PMOS are infact not in the schematic.

    1) How could I get them from the extracted view?

    2) How could I simulate the mismatch in those?

    Thanks, marco

    • Post Points: 20
  • Thu, Feb 19 2009 11:46 PM

    • Ling
    • Not Ranked
    • Joined on Tue, Feb 10 2009
    • Posts 4
    • Points 35
    Re: Leakage currents & mismatch Reply

    Hi,

    I don't know how to simulate the effect of this parasitics, but I know an case that have a very big leakage current, nearly 50mA.

    In this case, we put some p-sub taps around NMOS, but we lost the p-well mask for the NMOS, as a result, these NMOS were bult on the P-sub instead of the Pwell, then we have a very big leakage current

    • Post Points: 5
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Started by mb47 at 02 Feb 2009 12:09 PM. Topic has 1 replies.