we use Synopsys Star-RCXT for the extraction.
It seems that from a certain amount of pins the extractor doesn´t consider all off them. I´ve got a timeinterleaved structure with two equal parts. Extraction of just the single circuit and simulation in an upper schematic as the timeinterleaved structure delivers good results.
If I design the whole structure and simulate the extraction result with nearly two times the amount of pins it delivers signals outside saturation region (in time domain only for the second part of the structure) and FlipFlops which don´t switch due to power supply reasons. There are about 1500 VDD and VSS pins, so maybe there is some kind of upper boundary? :-) I´ve tried the same structure with a power grid on top and only few powerpins (about 8 each) and it works...