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 Mix-Singal system verification using VHDL and Verilog-AMS, pls help 

Last post Thu, Jan 29 2009 3:21 PM by TIRTH. 1 replies.
Started by lagy 19 Jan 2009 01:54 AM. Topic has 1 replies.
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  • Mon, Jan 19 2009 1:54 AM

    • lagy
    • Not Ranked
    • Joined on Sat, Jan 3 2009
    • Posts 2
    • Points 40
    Mix-Singal system verification using VHDL and Verilog-AMS, pls help Reply

    Our design is a mix-signal chip. It contains half digital part and half analog part.

    In order to have a more accurate system verification, we intend to use Verilog-AMS for the analog model and VHDL as the chip top.

    This is the first try for us to do such a verification.

    Anyon has idea whether this scheme is applicable or not?

    Any reference on similar implementation. 

    Thanks and Best Regards

    jh.
    • Post Points: 20

  • Thu, Jan 29 2009 3:21 PM

    • TIRTH
    • Not Ranked
    • Joined on Sat, Sep 20 2008
    • denton, TX
    • Posts 3
    • Points 15
    Re: Mix-Singal system verification using VHDL and Verilog-AMS, pls help Reply

     hi there,

    it is very much possible to do what you are trying to do. use cadence ams designer for this purpose and its better you use verilog instead of vhdl, or you can use system verilog, systemc as top level module.

     

    regards,

     tr

     
    • Post Points: 5
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Started by lagy at 19 Jan 2009 01:54 AM. Topic has 1 replies.