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 user opinion on SOCE hold fixing in 130nm and 90nm design 

Last post Mon, Feb 13 2006 11:16 AM by archive. 2 replies.
Started by archive 13 Feb 2006 11:16 AM. Topic has 2 replies and 1346 views
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  • Mon, Feb 13 2006 11:16 AM

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    user opinion on SOCE hold fixing in 130nm and 90nm design Reply

    We ran into some problem in hold fixinng in SOCE, not abel to fix all the violations. STA using Prime Time reported more violations than SOCE.

    Thanks.

    li siang


    Originally posted in cdnusers.org by lisiang
    • Post Points: 0
  • Fri, Feb 17 2006 2:16 PM

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    RE: user opinion on SOCE hold fixing in 130nm and 90nm design Reply

    Hi lisiang,

    Did SoC-E report hold violatons remained after running hold fixing?

    ie, do you think it was purely a timing correlation issue -or- a quality of results issue as well as a timing correlation issue?

    Thanks,
    Bob


    Originally posted in cdnusers.org by BobD
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  • Fri, Feb 17 2006 2:25 PM

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    RE: user opinion on SOCE hold fixing in 130nm and 90nm design Reply

    it is more of timing timing correlation issue. By default, PT report both setup and hold violation in OCV mode, ie for setup, fast slew prop. to the lauching flop and slow slew prop. to the capturing flop. SOCE timing optimzation (optDesign) was not able to handle both fast and slow slew prop. in the same run.

    li siang


    Originally posted in cdnusers.org by lisiang
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Started by archive at 13 Feb 2006 11:16 AM. Topic has 2 replies.