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 How to use vcs or vsim inside Cadence ADE 

Last post Thu, Nov 20 2008 11:03 PM by Germanicus2008. 0 replies.
Started by Germanicus2008 20 Nov 2008 11:03 PM. Topic has 0 replies and 966 views
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  • Thu, Nov 20 2008 11:03 PM

    How to use vcs or vsim inside Cadence ADE Reply

      Hi, there
    I am just on a mixed-signal project, sine we dont have nc verilog licence, what can I do to simulate a mixed-signal project in which both cadence schematic and Verilog HDL is used. When I asked the digital guys, they told me they use vcs or vsim to compile the HDL file. I wonder if it is possible for cadence to call other verilog compilers?



    Thanks.

    • Post Points: 5
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Started by Germanicus2008 at 20 Nov 2008 11:03 PM. Topic has 0 replies.