This is a valid question. Clock Tree Synthesis is a long-standing technique widely available in place and route tools whereby the tool is tasked with automatically matching the arrival time of the clock signal at each target in the clock network by building a tree of buffers and inverters distributed across the design. I would estimate that 90+% of designs implemented in SoC-Encounter use this approach.
Clock Mesh is an approach to consider when very tight control of arrival times of clock signals is mandatory. There are a few different approaches that fall into the Clock Mesh category, but essentially we seek to build a mesh-like strucutre across the chip with very regular drivers in the clock network. This regularity leads to very similar arrival times at each target (ie "low skew"). The tradeoffs associated with Clock Mesh are typically:
- Complexity of implementation
- Higher power consumption
- Greater routing resources used by the clock mesh
Hope this helps!