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 DRC violations after P&R 

Last post Wed, Aug 24 2005 7:30 AM by archive. 1 replies.
Started by archive 24 Aug 2005 07:30 AM. Topic has 1 replies and 1590 views
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  • Wed, Aug 24 2005 7:30 AM

    • archive
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    DRC violations after P&R Reply

    Hi all;
    I got some drc violations after P&R.
    Here are the descriptions about the problems. If anybody can take a look at it and give some advice, it will be much appreciated.

    Thank you
    Seonho


    1. Type 1 violation
    (1) Minimum metal distance rule between wide metals
    At first it is not wide metal. But, as via1 added to the metal,
    it becomes wide metal. But, P&R tool doesn’t consider this final
    structure as a wide metal. That’s how this violation took place.
    So, if we have option by which we can make the tool recognize this,
    this problem will be resolved.
    (2) As you can see, one metal route is in the core and another wide
    metal is in the RAM. Since the metal in the RAM is wide, wide metal
    distance rule should be applied. But P&R tool applied the normal metal
    rule. I think this is happening either because lef file of the RAM is
    not complete or RAM block is not flattened so P&R tool doesn’t
    recognize the final structure. So, could you tell me how we can resolve
    this problem?

    2. Type 2 violation
    (1) This is via farm rule violation. I think this happens
    because there is no such rule specified in the lef file.

    3. Type 3 violation
    (1) Minimum number of vias on a wide metal. Basically, I thought
    only the number is important. But, since HERCULES gives this error,
    I think the configuration or alignment is also important.
    But, in the lef file, no specification about the configuration is made.
    Could you tell me if we can handle this problem in P&R tool?


    Originally posted in cdnusers.org by semicond
    • Post Points: 0
  • Thu, Sep 15 2005 7:10 AM

    • archive
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    • Joined on Fri, Jul 4 2008
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    RE: DRC violations after P&R Reply

    Semicond,

    Here is an answer from Cadence engineering:

    #1.1 NR should recognize this as violation if the wide spacing rule (RANGE) rule is defined in LEF. If not, it could be a bug or the user used a very old version of NR where an option was required to support this.

    #1.2 NR should recognize this violation unless the RAM abstract is not properly defined or the setting in the LEF file, USEMINSPACING OBS ON. If this is set to on, then NR will use minimum spacing against obstruction.

    #2.1 The user answers his/her own question.

    #3.1 Which wide metal the user was talking about? Is it for special net? If it is, then the via gen rule might have not been defined properly. If it is in regular nets, then the LEF might have not contained MINCUT rule.


    Originally posted in cdnusers.org by Moderator
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Started by archive at 24 Aug 2005 07:30 AM. Topic has 1 replies.