Hi all; Originally posted in cdnusers.org by semicond
I got some drc violations after P&R.
Here are the descriptions about the problems. If anybody can take a look at it and give some advice, it will be much appreciated.
1. Type 1 violation
(1) Minimum metal distance rule between wide metals
At first it is not wide metal. But, as via1 added to the metal,
it becomes wide metal. But, P&R tool doesn’t consider this final
structure as a wide metal. That’s how this violation took place.
So, if we have option by which we can make the tool recognize this,
this problem will be resolved.
(2) As you can see, one metal route is in the core and another wide
metal is in the RAM. Since the metal in the RAM is wide, wide metal
distance rule should be applied. But P&R tool applied the normal metal
rule. I think this is happening either because lef file of the RAM is
not complete or RAM block is not flattened so P&R tool doesn’t
recognize the final structure. So, could you tell me how we can resolve
2. Type 2 violation
(1) This is via farm rule violation. I think this happens
because there is no such rule specified in the lef file.
3. Type 3 violation
(1) Minimum number of vias on a wide metal. Basically, I thought
only the number is important. But, since HERCULES gives this error,
I think the configuration or alignment is also important.
But, in the lef file, no specification about the configuration is made.
Could you tell me if we can handle this problem in P&R tool?