Although you can use the vhdl library, it would be best to obtain and use a verilog version of the library cells. This is because there could be a large performance impact due to having to transition through the language boundary for every cell. The library would be something provided by the vendor whose cells are being used.
Since you already have VHDL libraries, another method could be to have the netlist created in VHDL.
Let me know if this helps.