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 Estimated power consumption of a full custom digital IC design 

Last post Fri, Apr 25 2008 7:53 AM by archive. 2 replies.
Started by archive 25 Apr 2008 07:53 AM. Topic has 2 replies and 1171 views
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  • Fri, Apr 25 2008 7:53 AM

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    Estimated power consumption of a full custom digital IC design Reply

    I have drawn a full custom digital circuit using Cadence Virtuoso and have simulated it using Spectre. I wish to obtain the dynamic (including both switching and short-circuit) and leakage power components of the circuit. How do I estimate it for a given set of input stimuli. I also like to know as to how do I get to know the worst case delay of the circuit, for rising and falling transitions separately? Expecting your clear replies as I am quite new to full custom digital IC design.

    Thanks,
    Bala


    Originally posted in cdnusers.org by spbalan04
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  • Wed, Apr 30 2008 12:49 AM

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    RE: Estimated power consumption of a full custom digital IC design Reply

    Bala,

    Your question is broad and covers a series of tools. A lot more detail is needed to properly answer your question. In general, the flow can be split into the following parts:

    1. Extraction (QRC)
    2. Simulation (Sprectre, Ultrasim)
    3. Analysis (VoltageStore - IR/EM analysis)
    4. Litho effect on manufacturability and timing, if 65 nm or below.

    The best way to obtain support is to file a Service Request with Cadence or talk to your Cadence Account Executive. The solution that you are looking for cannot be adequately addressed in this forum.

    Luke Lang


    Originally posted in cdnusers.org by lukelang
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  • Wed, Apr 30 2008 4:58 AM

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    RE: Estimated power consumption of a full custom digital IC design Reply

    After drawing the transistor level schematic using Cadence Virtuoso and subsequent simulation using Spectre, I was able to see the current waveform. When I used Wavescan on the netlist (transistor level SPICE like netlist), I was able to see the power consumption in microWatts. But there were two power values. One, I think corresponds to the current flow when the circuit turned ON multiplied by the supply voltage. I think this might be the dynamic power component. Apart from this, there was another power component. I don't know whether this refers to the total power consumption as it was higher than the dynamic component. Could you kindly clarify? I haven't extracted the layout and the above figures are obtained before getting the layout.

    Thanks,
    Bala


    Originally posted in cdnusers.org by spbalan04
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Started by archive at 25 Apr 2008 07:53 AM. Topic has 2 replies.