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# regarding calculation of leakage current

Last post Fri, Oct 24 2008 2:19 AM by rkkhandelwal. 2 replies.
 Started by rkkhandelwal 23 Oct 2008 04:48 AM. Topic has 2 replies and 1796 views
• #### Thu, Oct 23 2008 4:48 AM

regarding calculation of leakage current
• Post Points: 20
• #### Thu, Oct 23 2008 9:30 AM

• Eric Gamble
• Joined on Tue, Oct 21 2008
• Hillsboro, OR
• Posts 4
• Points 80
Re: regarding calculation of leakage current
 Hi rkkhandelwal,What type of leakage current?  Gate leakage?  Subthreshold conduction?  Are you designing in CMOS?  Are you characterizing a single gate or a whole design?  How accurate do you need it to be?  If you want help, I'd encourage you to be as specific as possible. Here are some thoughts:1) If you have a large digital design block, and you are looking at the non-dynamic power, bias the thing up, get it in a known stable state, and stop the clocks.  Plot the current  until it reaches a stable state.  That is your static power dissipation, which included gate leakage, and subthreshold conduction.2) If you are looking at gate leakage for a process, bias a transistor and plot the dc current flowing into the gate.3) If you are looking at subthreshold conduction leakage, step through the possible inputs and output states and look at the drain current when the circuit is at steady state. These are all pretty generic.  To save a current in the analog design environment, use the menu option Outputs -> To Be Saved -> Select on schematic and click on the pin of the device that you want to plot the current.  Eric.
• Post Points: 20
• #### Fri, Oct 24 2008 2:19 AM

Re: regarding calculation of leakage current
 irst of all i m verymuch thankful to you that u reply on my post.actually i m working on mtcmos design tht is a low power circuit technique. so , i have to calculate standby mode power consumption .i have to do comparison between cmos and mtcmos leakage power consumption . presently i  m able to calculte only average power from cadence spectre simulator. presently i m working only small gates but i have to do it for a large digital network. if u can guide me further more in this regard then it will be very helpful to me . though now i will try ur suggestions and see what i can get from tjis. and i again want to say i m very thankful to u.   regards rohit khandelwalit bhu , varanasi(u.p.)india    Hi rkkhandelwal,What type of leakage current?  Gate leakage?  Subthreshold conduction?  Are you designing in CMOS?  Are you characterizing a single gate or a whole design?  How accurate do you need it to be?  If you want help, I'd encourage you to be as specific as possible. Here are some thoughts:1) If you have a large digital design block, and you are looking at the non-dynamic power, bias the thing up, get it in a known stable state, and stop the clocks.  Plot the current  until it reaches a stable state.  That is your static power dissipation, which included gate leakage, and subthreshold conduction.2) If you are looking at gate leakage for a process, bias a transistor and plot the dc current flowing into the gate.3) If you are looking at subthreshold conduction leakage, step through the possible inputs and output states and look at the drain current when the circuit is at steady state. These are all pretty generic.  To save a current in the analog design environment, use the menu option Outputs -> To Be Saved -> Select on schematic and click on the pin of the device that you want to plot the current.  Eric.
• Post Points: 5