Mudit,Originally posted in cdnusers.org by lukelang
You have raised some great questions. Power estimation and analysis is a complex topic but has huge implications. Under estimation of power will cause chip failure on the tester or in the system. Over estimation of power will be costly due to larger die size, more expensive package, and greater system cooling requirement.
As you have correctly pointed out, switching activity is a is a key component of dynamic power. Most designers try to get switching activity from simulation. The problem here is that most testbenches are written to detect design errors and may not reflect actual chip operation. Even if tests are written to simulation real-life operation, the simulation may take too long to reach the peak activity period. As a result, you might get local rather than global peak power.
Many designers estimate power dissipation with a combination of switching activity from simulation, measured power dissipation from previous designs, and some sort of power margin (fudge factor) to account for uncertainty.
Regardless of which method you use to estimate power, it is important to do it early in the design cycle so that you have the power architecture to meet your power requirements. Failure to meet the power requirement late in the design cycle is a sure way to blow the project schedule.
Does anyone else have any comments?