The "rand_bit_stream" cell in the ahdlLib library has both spectreHDL and VerilogA representations; you can instantiate the symbol in a schematic and use it in your design that way. When you netlist, you will pick up either of the versions mentioned depending on your switch view list or your configuration (using the Hierarchy Editor) which will control which view is used by the netlister when expanding the design. When you place an instance of the rand_bit_stream, you can supply various parameters to it, such as the logic high and low voltage levels, the period and the risetime and falltime. The "seed" parameter can also be supplied - since it will always default to the same value, thr pseudo-random sequence will be repeatable from one simulation to the next.
I hope that this answers your question.