I am working on implementing a block using FE. Usually, after I finally achieve timing-closure, I will dump/save verilog netlist and verilog-In the netlist into Cadence dfII to create new schematic for the block, which will reflect the netlist changes from IPO/CTS. However, at this time, front-end team has a customized top level schematic: lower level symbols are located in proper places; all the wire connections are hand-drawn and clearly labeled... They love it so much and don't like to lose it. So, they asked me whether or not it is possible to tell FE only put changes to lower level modules duing CTS/IPO and keep top level untouch even during IPO/CTS, then, we only need to verilog-in the lower level module into dfII and top level schematic that they love will survive.
Any body has tried the similar or have a good idea to achieve this?