Home > Community > Forums > Hardware/Software Co-Development, Verification and Integration > using command ncverilog cause hang issue


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 using command ncverilog cause hang issue 

Last post Tue, Nov 11 2008 5:41 AM by Inan ERDEM. 2 replies.
Started by Jack Lee 08 Oct 2008 12:01 AM. Topic has 2 replies and 3779 views
Page 1 of 1 (3 items)
Sort Posts:
  • Wed, Oct 8 2008 12:01 AM

    • Jack Lee
    • Not Ranked
    • Joined on Wed, Oct 8 2008
    • Posts 5
    • Points 100
    using command ncverilog cause hang issue Reply
    Hi, I am Jack.

    I have something to verify about the ncverilog command.

    I write the ncverilog command to compile and simulate my design:ncverilog   abc_tb.v -f abc_tb.f -l abc_tb.log  +ncelabargs+"-timescale 1ps/1ps" +access+rw(abc_tb.f is the filelist which contains all files required for this design) I face hanging issue while running simulation, when I remove the option +access+rw, the hang issue can be avoided.Why this can be happened?I have tried out with other tools like VCS, I have not experienced this type of issue, thanks for giving me some advices.
    • Post Points: 35
  • Mon, Oct 27 2008 12:23 PM

    • Mickey
    • Top 100 Contributor
    • Joined on Mon, Oct 13 2008
    • Austin, TX
    • Posts 77
    • Points 1,315
    Re: using command ncverilog cause hang issue Reply

     Hi Jack,

     I suspect you are encountering a zero-delay loop race condition in the code.  When the -access option is used, under the hood the result is the turning off of optimizations designed to have the simulator perform as efficiently as possible. When optimizations are enabled/disabled the result can be a reordering of events within the various time slices.  In a race-free design this reordering will have no effect on the result of the simulation.  If there are races in the design, however this reordering can and often does highlight situations in the code that are dependent on a certain evaluation order to produce the desired simulation effects.  Because different simulators use different algorithms to process events, changing from one simulator to another can also highlight code that is dependent on a given evaluation order.

    How to find the race?  That's really the million dollar question.  Unfortunately it's not always easy.  One method would be to add "+nclinedebug +gui" to your command line to bring up the simulation in an interactive gui.  Bring up the source browser and hit the play button and take note of the increasing time and delta cycles.  When you note that time has stopped and only delta cycles are increasing you know that you have encountered the zero-delay loop.  Thereafter hit the pause/play button until you can determine the section that code that is getting updated and reupdated during the loop.

    Hope that helps.


    • Post Points: 5
  • Tue, Nov 11 2008 5:41 AM

    • Inan ERDEM
    • Not Ranked
    • Joined on Tue, Nov 11 2008
    • Istanbul, 00-TR
    • Posts 4
    • Points 35
    Re: using command ncverilog cause hang issue Reply

    Hello Jack and Mike,

     I am facing the same problem as yours and I am using Synopsys's STIL Direct Pattern Validation flow, which means I am taking the patterns generated by Tetramax and simulating using NCSIM and having that same hanging issue. My problem is that I can not disable access since it is used by PLI routins to force values during simulations. Is there any other way of getting rid of that haning issue other than disabling access?

    • Post Points: 5
Page 1 of 1 (3 items)
Sort Posts:
Started by Jack Lee at 08 Oct 2008 12:01 AM. Topic has 2 replies.