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 using command ncverilog cause hang issue 

Last post Fri, Nov 21 2008 4:56 PM by Inan ERDEM. 9 replies.
Started by Jack Lee 08 Oct 2008 12:00 AM. Topic has 9 replies and 10377 views
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  • Wed, Oct 8 2008 12:00 AM

    • Jack Lee
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    using command ncverilog cause hang issue Reply
    Hi, I am Jack.I have something to verify about the ncverilog command.

    I write the ncverilog command to compile and simulate my design:ncverilog   abc_tb.v -f abc_tb.f -l abc_tb.log  +ncelabargs+"-timescale 1ps/1ps" +access+rw(abc_tb.f is the filelist which contains all files required for this design) I face hanging issue while running simulation, when I remove the option +access+rw, the hang issue can be avoided.Why this can be happened?I have tried out with other tools like VCS, I have not experienced this type of issue, thanks for giving me some advices.
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  • Mon, Oct 27 2008 10:06 PM

    • Jack Lee
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    RE: using command ncverilog cause hang issue Reply
    Hi Mickey,

    Thanks for you information.
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  • Tue, Nov 11 2008 6:05 PM

    • Jack Lee
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    RE: using command ncverilog cause hang issue Reply
    My hanging issue just solved when I detect that there is “non-stop” looping in my design codes. You just need to use run –step to manually run your design step by step until you have detected the non-stop looping occurred. Just refer my attachment about my solving and explanation. Thanks
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  • Wed, Nov 12 2008 9:01 AM

    • Mickey
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    Re: RE: using command ncverilog cause hang issue Reply

    Hi Inan,

    The introduction of PLI is another layer of complexity to determining the cause of a hanging simulation.  The way the simulator works with a PLI is when a PLI is encountered, control is passed to the PLI to execute it's function.  Once the PLI completes its code processing, control is given back to the simulator. So another possible source of the hang could be the coding within the PLI.

    I would encourage you to check with Synopsys to make sure that you have the latest version of their PLI.  I'd also make sure that the latest IUS version is being used.  You should also open a service request with Synopsys as well as our support team (support@cadence.com) and include a testcase so that the situation can be investigated.

    Best regards,
    Mickey 

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  • Fri, Nov 14 2008 8:52 AM

    • Mickey
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    Re: RE: using command ncverilog cause hang issue Reply

    Hi Inan,

    In regard to the hang you are seeing with using the Synopsys STIL PLI, you might try to use the nbasync command line option in your simulation as follows: 

    if you are using ncvlog/ncelab/ncsim or irun add -nbasysnc to the ncsim or irun command line.

    If you are using ncverilog to run the simulation add +nbasync.

     

    Basically this options changes the order in which synchronization callbacks are executed within the event cycle.  Give it a try and let us know if that helps.

    Best regards,
    Mickey

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  • Sat, Nov 15 2008 5:55 PM

    • Inan ERDEM
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    Re: RE: using command ncverilog cause hang issue Reply

    Hi Mickey,

     First thanks for your explanations and help.

     I would like to clarify one point: In my situation the time is frozen and delta cycles are not also counting up. Simulator doesnt respond to my pause command(I used both the pause button and ctrl+C).It only come out of its infinite run with multiple ctrl+Cs and that multiple ctrl+Cs are causing the simulator to terminate.

     When I try to do line-by-line debugging very close to the hanging time, I lost the yellow arror(it gets grayed out) somewhere close to that hanging time and I can't know where is the last statement executed before entering that infinite loop.It could be somewhere in one of those c library.

    If it was a delta cycle issue, it would be much and much more easy to debug as I can trace the code and see the feedback path, but now I can do simply nothing other then givin multiple ctrl+C commands end then let the simulator terminate.Therefore even if I enable a breakpoint of 1 delta cycles, simulator hangs before even a single delta cycle!!!!

    By the way, +nbasync option couldn't solve the issue, but it chaned the hanging time point. When I recompile the same design at different times, it also changes the hanging time point as well.

     How can I also check the compatibility of STIL DPV libraries, simulator and the compiler that I use for my .c files' compilation.

     Regards,

     Inan.

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  • Sat, Nov 15 2008 6:05 PM

    • Inan ERDEM
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    Re: RE: using command ncverilog cause hang issue Reply

    Hi again Jack,

    The answer of this question is very very important for me: How Simulator was hanging in your situation

    1. Was it a delta-cycle issue, in which time was stopped but delta cycles were counting up?

    2. Was it a frozen issue, in which both time and delta cycles were not increasing and simulator couldn't be stopped with a single ctrl+C command?.

     My current situation is the second one, in which I can do nothing : I can not even pause the simulator with a single ctrl+C. What I can do is just pressing ctrl+C multiple times and simulator terminates.So I can not do debugging I can not know where was the last statement before entering the hanging state .....

     Regards,

     Inan.

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  • Sun, Nov 16 2008 5:54 PM

    • Jack Lee
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    RE: RE: using command ncverilog cause hang issue Reply
    Hi Inan,

    Mine one is first situation.

    Regards,

    Jack
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  • Mon, Nov 17 2008 2:26 PM

    • Mickey
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    Re: RE: using command ncverilog cause hang issue Reply

     Hi Inan,

    It's hard to pinpoint the problem given what you are seeing with the simulation.  At this point I would encourage you to do the following:

    1)  make sure that you are using the latest subversion for the version of the IUS simulator being used.  You should also check with Synopsys to see if there is a more recent version of the stil pli.

    2)  Once you've determined that you are using the latest tools and you are continuing to see the problem start peeling away layers of items to see if the problem can be pinpointed.  Remove sdf annotation if that is being included with the sim.  What command line options are being used?  If at all possible remove the pli from the simulation.  If that is not possible try to zero out the function calls within the veriuser.c file and recreate the libpli.so.

    3)  open up a service request with Cadence customer support (support@cadence.com) as well as Synopsys support.

    Best regards,

    Mickey

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  • Fri, Nov 21 2008 4:56 PM

    • Inan ERDEM
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    Re: RE: using command ncverilog cause hang issue Reply

    Hello Mickey,

     Thank you for your help, It seems that one/some of the internal feedback loops in my design is causing this issue such that one of the C function from some of the shared libraries provided by Synopsys/Cadence is going into an infinite loop.

    At the moment both Synopsys and Cadence asks for a test case, but unfortunately I dont have time and it is hard to send Synopsys f iles to Cadence or wise versa.

    I am trying to break those internal loop one by one to see which one is causing the problem and then I will try to implement a sequential bypass when in ATPG mode.

     With my best wishes,

    Inan.

    • Post Points: 5
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Started by Jack Lee at 08 Oct 2008 12:00 AM. Topic has 9 replies.