I am new to CIS capture design. I made a simple VCO IC circuit which I am interested in testing. I made the circuit and then created a netlist where one error was that there is no template for u2 and it is ignoring it. Then I tried to run the circuit simulation and got the error " node n91773 floating" I am unable to resolve this issue. This is one of the two nodes of a capacitor. The other node of the capacitor is also giving me the same error. Any help is appriciated.