Home > Community > Forums > PCB Design > SI-via parameterization n probing of topology

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 SI-via parameterization n probing of topology 

Last post Thu, Sep 25 2008 1:18 AM by MAAC. 2 replies.
Started by MAAC 22 Sep 2008 09:02 PM. Topic has 2 replies and 1700 views
Page 1 of 1 (3 items)
Sort Posts:
  • Mon, Sep 22 2008 9:02 PM

    • MAAC
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Bangalore, Karnataka
    • Posts 195
    • Points 3,620
    SI-via parameterization n probing of topology Reply

    hi,

    Has anybody tried the via modelling in SI. I am interested in changing the RLC of via in sigxp...is it possible, can anybody explain me on this...License-SI XL.

    Also probing of topology, is it possbile or necessary to see the response of the toplogy at different instant.. as per my knowledge the respone should be from pin 2 pin......is it right...

    • Post Points: 20
  • Wed, Sep 24 2008 9:17 AM

    • Khurana
    • Top 25 Contributor
    • Joined on Thu, Aug 14 2008
    • Posts 238
    • Points 3,315
    Re: SI-via parameterization n probing of topology Reply

     Allegro SI has the ability to allow you to look at the via model and change the specifics.  Go to Analyze > Library > double click on the .IML file > change type to Via > click on Edit button.  This will launch Via Model Generator which may be used.  If you click on Text Edit button then a text editor is launched which shows the spice ckt content of the via in question which may be modified.

    To probe a topology at a location other than the driver or receives you may add a dummy probe.  It's in one of the Cadence supplied library files.   Add by going to Edit > Add Part.

    • Post Points: 20
  • Thu, Sep 25 2008 1:18 AM

    • MAAC
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Bangalore, Karnataka
    • Posts 195
    • Points 3,620
    Re: SI-via parameterization n probing of topology Reply

    Hi,

    thns khurana.

     

    i got it... isn`t possible to get the information of RLC values of pads as we get RLC values of net using show parasitics cmd..

     

     

    • Post Points: 5
Page 1 of 1 (3 items)
Sort Posts:
Started by MAAC at 22 Sep 2008 09:02 PM. Topic has 2 replies.