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 Finding area of designed IC 

Last post Mon, Sep 22 2008 9:28 AM by skillUser. 1 replies.
Started by NathS 21 Sep 2008 12:01 AM. Topic has 1 replies and 1845 views
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  • Sun, Sep 21 2008 12:01 AM

    • NathS
    • Not Ranked
    • Joined on Sun, Sep 21 2008
    • Surrey, British Columbia
    • Posts 3
    • Points 60
    Finding area of designed IC Reply

    Hi, I'm very new to this program (Cadence Custom IC design).

    I'm using this program for a course in my university, and it is on a UNIX (solaris 8) environment.

    The version of Virtuoso (i think) is 5.00.

    As instructed, I made a library and designed inverter (cell name = inv_N1P1) by having one Nmos and one Pmos.

    Now the question that prof gave is 'what is the area of this cell?'

    Can anyone help me on finding the area?

    I've never used UNIX and neither this program... I'll appreciate any help.

    • Post Points: 20
  • Mon, Sep 22 2008 9:28 AM

    • skillUser
    • Top 10 Contributor
    • Joined on Fri, Sep 19 2008
    • Austin, TX
    • Posts 2,587
    • Points 15,915
    Re: Finding area of designed IC Reply

    Hi,

    You can find the area of the cellview using SKILL, for example, with the design window open,  type the following SKILL in the CIW (the command interpreter window):

      geGetEditCellView()~>bBox

    This gives you the bounding box of the cellview from which the cellview area can be calculated. An example might be:

      bbox = geGetEditCellView()~>bBox
      times(
      abs(apply('difference mapcar('car bbox)))
      abs(apply('difference mapcar('cadr bbox)))
      )

    However, is the question asking the area of the devices, or the overall cell?

    Regards,

    Lawrence.

    • Post Points: 5
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Started by NathS at 21 Sep 2008 12:01 AM. Topic has 1 replies.