KulPrashant,Originally posted in cdnusers.org by lukelang
Power analysis is an estimation of power dissipation, both dynamic and static, of the chip in various operating modes. IR drop analysis deals with the chip's current draw and the associated voltage drop across the power grid, power switches, etc. Since gate delay depends greatly on the applied voltage, it is very important to make sure that a sudden current draw does not reduce the voltage and slow down the gate to the point of circuit failure.
Static power analysis is the calculation of leakage power. A cell dissipates leakage power when voltage is applied even if it is not switching. As the process geometry shrinks, leakage power is becoming a greater percentage of a chip's overall power dissipation. It is something that we cannot ignore. Dynamic power consists of power dissipated inside a cell (mostly due to short-circuit current during switching) and power dissipated to charge/discharge net capacitance. Dynamic power is a function of voltage, toggle rate, and net loading.
Static IR drop analysis is a first-order approximation. It uses the total power dissipation to calculate a constant current draw. This current is then multiplied by the equivalent resistance of the power network to arrive at the voltage drop. As we know, a circuit does not draw constant current. Current draw increases when a cell is switching. (See dynamic power above.) When a group of cells is switching at the same time, it draws a lot of current at that moment in time. Dynamic IR drop analysis deals with the voltage drop of these current surges.
For power analysis, each cell's power dissipation has been characterized in the library (.lib) file. For leakage power, the EDA tool simply adds up the leakage power of each cell. (Note: Leakage power is usually state dependent, so there is a bit of work here.) For dynamic power, the EDA tool either estimates net capacitance before P&R or calculates net capacitance after P&R. The designer has to provide the toggle rate. This can be based on educated guess, experience, simulation, or emulation. The accuracy of the power analysis depends directly on the accuracy of net capacitance and toggle rate.
Power analysis must be considered very early in the design cycle. Typically, 80% of a chip's power is determined at the RTL stage. After that, a design team can only impact 20% of the power. Here are some of the questions that a design team should answer at the architectural stage:
- Which voltage supply should we use?
- Can we achieve lower power with more than one voltage supply?
- Do we have inactive blocks that we can shut off to reduce leakage power?
- If we shut off blocks, are there registers that we have to retain the state?
- Do we have blocks that can run at slower rate in certain modes? Can we reduce the voltage during those modes?
The Cadence low-power solution has been architected to address all of the above issues and more. I would encourage you to visit www.cadence.com/lowpower. Also, CDNLive 2007 Silicon Valley will be starting in less than a week. Low-power design is a major theme of the conference. I will be conducting a low-power techtorial on Sunday, 9/9/07, where the attendees will get hands-on experience with the Cadence low-power solution. There will be lots of papers dealing with all aspects of low-power design. Some will even address design and tapeout experience using the Common Power Format. It should be a great opportunity for anyone interested in low-power design to learn a lot in a short period of time.