I ran a post-layout C-only RCX extraction to generate an av_extracted cell and probed each of the nodes of my layout to get the capitances at each node. The weird thing is if I use ideal caps with the values of these capacitances and place them on an identical schematic and run simulations, the results are vastly different than what I get if I generate an av_analog_extracted cell and run a simulation through config. I've made sure the schematic from config is different from the one that I added ideal caps to. Why is there this discrepancy? Is the capacitance probed from av_extracted a distributed capacitance that cannot be simply modeled by an ideal cap placed at the corresponding node of the schematic?