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 Using Verilogin 

Last post Thu, Sep 18 2008 6:39 AM by dinac. 5 replies.
Started by dinac 16 Sep 2008 09:52 AM. Topic has 5 replies and 3427 views
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  • Tue, Sep 16 2008 9:52 AM

    • dinac
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    • Joined on Tue, Aug 5 2008
    • Posts 9
    • Points 105
    Using Verilogin Reply

    hi all, 

    I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.  

    I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"

    Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell?  Is my flow right? I wanted to do a mix-simulation.

    please help

    Thanks a lot........

    • Post Points: 20
  • Wed, Sep 17 2008 12:47 AM

    • vjain
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    • Points 40
    Re: Using Verilogin Reply

    Your standard library should be included in the Library manager before VerilogIn. The name of the "Reference-Library" is the name of the standard cell library as mentioned in Library manager.

    • Post Points: 20
  • Wed, Sep 17 2008 1:28 AM

    • dinac
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    • Joined on Tue, Aug 5 2008
    • Posts 9
    • Points 105
    Re: Using Verilogin Reply

    hi vjain,/all

    Thanks for your reply,.

    i did define the library ".lib" location in cds.lib. but when i parse this verilog netlist i get few errors.

    VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    VerilogIn: *W,101 => Could not find symbol master for instance XY .Functional view won't have this instance.

    Please help

    thanks

     

    • Post Points: 20
  • Wed, Sep 17 2008 2:44 AM

    • vjain
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    Re: Using Verilogin Reply

    VerilogIn: *W,31 => Module X in FSM_file  not defined.Module FSM_file will be imported as functional.

    This is because there is come submodule of FSM_file which cannot be made with the information you have given. Functional import is done whenever the verilog file has behavioral description.

    Point to remember: Your verilogin file should be gate level netlist only. No behavioral or dataflow models should be there. I hope this should help.

    • Post Points: 20
  • Wed, Sep 17 2008 8:02 AM

    • dinac
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    • Joined on Tue, Aug 5 2008
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    Re: Using Verilogin Reply

    Thanks for your message....

    The Module X  referes to one my standard cells.

    I still have doubt in the Reference Library part, i do not see any cells in the Library Manager for this Reference Library, is it normal?

     thanks

    • Post Points: 5
  • Thu, Sep 18 2008 6:39 AM

    • dinac
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    • Joined on Tue, Aug 5 2008
    • Posts 9
    • Points 105
    Re: Using Verilogin Reply
    Hi

    Thanks for your reply.
    I guess i solved it

    1. Reference Library "CDK"

    2. -V option i provided the link of the standard-cell file in verilog format. ".V"


    I found few errors, mentioning the verilog
    " Verilog definition for module AND2 was not found. Using lib 'techlib' cell 'AND2' view 'symbol' as its symbol.

    But i guess I could discard this.


    Thanks a lot Again

    cheers
    dinac
    • Post Points: 5
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Started by dinac at 16 Sep 2008 09:52 AM. Topic has 5 replies.