I am new to cadence, i am trying to simulate the digital-control logic along with the analog in cadence.
I synthesised my vhdl code to verilog netlist using design-compiler, using standard-cell library ".lib"
Now I am trying to import this into the cadence using verilogin. I did not understand the "Reference-Library" in verilogin . Should I create this Reference library from the .lib format standard-cell? Is my flow right? I wanted to do a mix-simulation.
Thanks a lot........