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 ECO Flow with the Clock Gating Flow 

Last post Thu, May 3 2007 8:22 PM by archive. 0 replies.
Started by archive 03 May 2007 08:22 PM. Topic has 0 replies and 1305 views
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  • Thu, May 3 2007 8:22 PM

    • archive
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    ECO Flow with the Clock Gating Flow Reply

    During clock gating, all the synchronous load enabled registers are going to get gated clock. If suppose, during ECO, if you want to make one synchronous load enable flop as a normal flop, then the clock has to reach the flop, without going through the ICG element. Do you have any recommendations on CTS or implementation side, in this kind of a scenario?


    Originally posted in cdnusers.org by gukumar
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Started by archive at 03 May 2007 08:22 PM. Topic has 0 replies.