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 senthesize sub-module  

Last post Thu, Aug 21 2008 3:23 AM by designer. 0 replies.
Started by designer 21 Aug 2008 03:23 AM. Topic has 0 replies and 2108 views
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  • Thu, Aug 21 2008 3:23 AM

    • designer
    • Not Ranked
    • Joined on Wed, Aug 13 2008
    • Gratkorn, Styria
    • Posts 9
    • Points 105
    senthesize sub-module Reply

    Hi all,

    I want to synthesize a design with RC but with different constraints for different blocks. The top-level includes memory and analogue models and the digital part. I want to keep the interface for all the blocks in the top-level even when they are unconnected. For this I set this attribute and it works fine: set_attribute write_vlog_unconnected_port_style  full.

    But some of the sub-modules in the digital block have constant inputs (connected to 0 or 1). For these blocks I would like that the RC removes the constant input port, propagate the constant and optimizes the logic. Currently it does not do that -maybe- because of the changing the above attribute. On the other hand when I try to do a synthesis for sub-blocks it fails since it cannot find the sub-design. I use the following command to synthesis a sub-module with name top_dig_mod1:

    synthesize  -to_generic  /designs/cai_kll_beaver_top/subdesigns/top_dig_mod1

    Any idea how to do this!


    Thank you for your comments in advance!



    • Post Points: 5
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Started by designer at 21 Aug 2008 03:23 AM. Topic has 0 replies.