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 Best way to generate timing .libs for digital users of analog blocks? 

Last post Fri, Aug 22 2008 5:43 AM by ScreenName. 1 replies.
Started by duroid 19 Aug 2008 08:03 AM. Topic has 1 replies and 3183 views
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  • Tue, Aug 19 2008 8:03 AM

    • duroid
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    Best way to generate timing .libs for digital users of analog blocks? Reply

    I recently finished a PLL design and it seems to work well in simulation. I could manually create a LEF file quite easily, but now I need to create a timing library (.lib) for downstream digital users, so that clock tree synthesis etc. will do the right thing. But I have no idea how to do this - I couldn't find any mention of it in any documentation I have, and they couldn't find anything in the SOC Encounter documentation.

     What's the correct way to generate a timing library given an analog block layout, SPICE netlist, etc..?


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  • Fri, Aug 22 2008 5:43 AM

    • ScreenName
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    Re: Best way to generate timing .libs for digital users of analog blocks? Reply


     There is a lot information which can be in the .lib.

    The pertinent informations depends on the constraints to respect on the block at the higher (or top) integration, to use STA engine and allow optimizations.

    Ususally, an analog IP which have timing constraints is characterized (Memory, standards cells, customs digital block) and a .lib is generated (with a perl script, or another way). If no timing constraints have to be  respected, the mimimal informations in the.lib are the pin out section, without timing/power section.

    Ususaly, an unconstrained analog IP is delivered as LEF/Lib and the .lib contains :

    - pin out (mandatory, aligned with verilog module)

    - max capacitance/trans/etc (design rules) values (not mandatory, but helps place/route, or synthesis to correct and/or to anticipate capacitance value).

    The minimal .lib is :

     library (name) {
    technology (name) ;/* library-level attributes */
    time_unit : unit ;
    voltage_unit : unit ;
    current_unit : unit ;
    pulling_resistance_unit : unit ;
    leakage_power_unit : unit ;
    piece_type : type ;
    piece_define (”list”) ;
    in_place_swap_mode : match_footprint |
    no_swapping ;
    library_features (value);
    simulation : true | false ;
    cell (name1) {/* cell definitions */
    cell information (pin/timing/power table)


    You can create a .lib with a copy/paste from an existing file, and replace cell/pin etc.. section.

     Or create a perl script to do it more automatically, i don't know (and didn't see) an official tool to create it easily.

    All explanation on liberty syntax are given in the User guide of Library compiler, i found a version here :


    To check your library syntax, you can use a synthesis or place and route tool and check warning/error at read_lib step. Although, library compiler is done for that (check, and translate .lib).








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Started by duroid at 19 Aug 2008 08:03 AM. Topic has 1 replies.