Thank you for your reply!
Now the problem is: in the soc encounter, I checked that no wire extension at pins and all wires just routed to the edge of the cell. When I imported the stream file into cadence, it passed DRC check, but I found that the path properties, for some paths, the begin/end extension value is 0, but for other paths, they are non-zero, also the type, some are flush, and others are variable which enable the begin/end extension value to be edited.
I don't know why did the wire not extend in the soc encounter (I did not find extension), but do extend in cadence and magic? How can I solve this problem?