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 Creating a master slave current mirror 

Last post Mon, Oct 20 2008 1:07 PM by skillUser. 1 replies.
Started by SiTel JU 14 Aug 2008 06:27 AM. Topic has 1 replies and 2799 views
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  • Thu, Aug 14 2008 6:27 AM

    • SiTel JU
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    • Joined on Wed, Aug 13 2008
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    • Points 20
    Creating a master slave current mirror Reply
    Hi, Is it possible to make for example a current mirror in a master slave kind of way? What I mean is this: can you say to the slave transistor to copy the width and length of the master transistor. Doing so would mean that if you change the w and L of the master the slave follows. Thanks.
    • Post Points: 20
  • Mon, Oct 20 2008 1:07 PM

    • skillUser
    • Top 10 Contributor
    • Joined on Fri, Sep 19 2008
    • Austin, TX
    • Posts 2,587
    • Points 15,915
    Re: Creating a master slave current mirror Reply

    One way to do this is to use a design parameter for the W and L using the same parameter for each transistor, e.g. parameters cmL and cmW - the values for these could be set in the simulation environment (ADE).

    Design variables are probably the way to go for this, and this would give you the added benefit of being able to run parametric analysis on the cmL and cmW parameters.

    An alternative might be to create an extra level of hierarchy so that you have at least these two transistors in a new cell. On the transistor instances you would use the pPar() function to refer to a named parameter on the parent (again let's say cmL and cmW), for example pPar("cmL") for the "l" (ell) parameter of both instances, and pPar("cmW") for the "w" parameter on each instance. When you create a symbol for this new cell (Design -> Create Cellview -> From Cellview) the automatic symbol generator will automatically create the two CDF parameters so that when you place an instance of the new cell, these parameters are present on the Add Instance for, or the Edit Object Properties form.

    Regards.

    • Post Points: 5
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Started by SiTel JU at 14 Aug 2008 06:27 AM. Topic has 1 replies.