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 Disable clock gating check for a module. 

Last post Sat, Aug 9 2008 1:23 PM by Tongju. 0 replies.
Started by Tongju 09 Aug 2008 01:23 PM. Topic has 0 replies and 2996 views
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  • Sat, Aug 9 2008 1:23 PM

    • Tongju
    • Top 200 Contributor
    • Joined on Mon, Jul 14 2008
    • San Jose, CA
    • Posts 38
    • Points 505
    Disable clock gating check for a module. Reply

    For a FE_placed&routed block reported no timing violation, the sign-off tool (PT) catched several huge timing violations (>10ns) on paths  from top level input pins to dff "d" pins.

    The issue traced back into a constraint "set_disable_clock_gating_check [get_cells {data_path/fifo/*}]". If I commented out this line from SDC file, then, FE saw those violations on in2reg pathes plus more pathes that are real clock gating path and should be disabled by the constraint.

    I don't understand why the set_disable_clock_gating_check comand will disable pathes in the in2reg group. looks like PT is doing the right thing by not disabling them (the same SDC file, therefore, the same constrains have been used in PT).  Did anybody see the similar issue? How can I tell FE to only disable the real clock gating path for a sub-block? If I specify the individual stdcell pins like "a/b/c" in nand/nor gates after the set_disable_clock_gating_check, it works fine for me. But I try to avoid to expand the "data_path/fifo/*" all the way down into the individual nand/nor stdcell pins since there are quite few such kind of constraints coming from front-end group.

     Thank you for your advice!

    Tongju

    Tongju

    • Post Points: 5
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Started by Tongju at 09 Aug 2008 01:23 PM. Topic has 0 replies.