Home > Community > Forums > Digital Implementation > PVT corner for worst case power analysis

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 PVT corner for worst case power analysis 

Last post Tue, Feb 6 2007 9:20 PM by archive. 6 replies.
Started by archive 18 Oct 2006 07:37 AM. Topic has 6 replies and 4839 views
Page 1 of 1 (7 items)
Sort Posts:
  • Wed, Oct 18 2006 7:37 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    PVT corner for worst case power analysis Reply

    Hello,

    I am not sure about what PVT corner I should use for worst case power analysis. I have identified two things in LIB files which are affected by PVT corner selection and affects power analysis:

    • K_factors for internal and leakage power;

    • Transition time.

    Temperature selection is ok! When we increase temperature we increase power consumption since both k_factors and transition time are directly proportional to temperature (power consumption of a cell depends on input transition time)

    The problem is for process and voltage selection:

    • Transition time decreases when we increase operating voltage (inversely proportional), in contrast of k_factors. So, I should select low or high voltage for worst case power analysis?

    • Transition time increases when we increase process value (directly proportional), in contrast of k_factors. So, I should select low or high process for worst case power analysis?

    Besides that, most of LIB files describes PVT corners only for STA and these corners are different for power analysis. So, it is needed define new corners in LIB files to perform worst case power analysis?

    Anyone can help me?
    Thanks in advance...

     


    Originally posted in cdnusers.org by clsantos
    • Post Points: 5
  • Thu, Oct 19 2006 10:13 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply

    I can certainly commiserate with you, my libraries are also setup for timing PVT points.

    Can I ask how accurate do you need your power estimate to be?

    In my experience, the inaccuracies in things like activity estimation, library data etc will tend to make the values measured with real silicon somewhat different to the pre-tapeout estimations (and even more different to RTL level estimation of power). What I do know however is that the relative saving of using a technique will be accurate between the estimation and the silicon.

    I know some tools allow values for P V & T to be set independent of the actual library fixed points, but I'm not sure if this is available in all Cadence tools.

    Chris


    Originally posted in cdnusers.org by Chris_Byham
    • Post Points: 0
  • Thu, Oct 19 2006 11:17 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply

    I am using simulation based analysis (with VCD files) because I think that is the most accurate analysis which is possible to perform using Encounter. Is it right?
    I know that any gate-level analysis will result in a power estimation somewhat different to measured values, but I think it is the best power estimation I can do at this design step. I intend to use this type of analysis to optimize power consumption once, as you have said, relative power savings will be valid in real silicon measurements.
    I tried overcome the problem of existing only PVT corners for timing in my LIB files by creating a new “dummy” LIB file just to specify power PVT corners. And it seems be ok!
    But my main problem is identify the right corner values for process and voltage to perform a safe power analysis. As I have stated in previous message, choosing best/worst values for voltage or process increases power through transition time but at the same time decreases power through k_factors, and vice-versa...
    So, it is better chose best or worst values for process and voltage to guarantee a safe power analysis?


    Originally posted in cdnusers.org by clsantos
    • Post Points: 0
  • Fri, Oct 20 2006 4:10 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply

    Simulation based analysis is by far the most accurate, but care is needed to ensure that you really have accurate use-cases for your block or chip in simulation.

    For example, I'm heavily involved with SoC integration, and although my team has testcases for IP blocks in the chip, these are typically only stressing the interface so we can ensure the integration is correct. It is less common for us to run simulations stressing each IP to ensure that it is performing it's own internal functions correctly (really depends on the source and complexity of the IP: I might test a Uart to the fullest extent, but a DSP that has been used on other products may only have a brief interface test). Thus if I were to use these sims as a basis for power-analysis, I may or may not get an accurate picture of the power consumption. So I tend to have to base my analysis on statistical analysis.

    As for which point to use for the actual analysis, yes I understand your problem. I don't think there is a right or wrong answer. I personally run my analysis at the worst-case timing PVT point, and don't worry if this is the worst power point. If I run all of my analysis at the same operating conditions, then the effect of design changes is surely valid. Also, since both my synthesis and layout tools are using this PVT to do optimisation for timing, then it makes sense to base all of my analysis here.

    Of course, if you are trying to see what effect making the design [i]high-Vt and std Vdd[/i] compared to [i]low-Vt with reduced Vdd[/i], then you could well see "savings" which are caused by the different operating points.

    You say that you've tried making dummy PVT points that match (suspected) power corners rather than timing corners. Can you run your analysis and tell us what difference P, V and T have on estimated dynamic and static power? My own gut feel is that the power increase caused by higher transition times will be less than that caused by higher voltages since power is just proportional to frequency, but is proportional to the square of the voltage.

    Chris


    Originally posted in cdnusers.org by Chris_Byham
    • Post Points: 0
  • Fri, Oct 20 2006 1:14 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply

    I agree with you that simulation based analysis depends a lot on used testcases. I think is a good idea develop specific testcases for power analysis.

    Concerning PVT for power analysis, I think if you have a power constraint, for example, you need to know if your design can reach this constraint and so worst case power consumption is important.
    In addition to that, worst case power analysis will give you the worst case IR drop and as far as I know it is needed to run STA considering this worst case IR drop (I have another doubt concerning STA using results of IR drop analysis, but I will post it in another topic).

    Your felling seems to be correct, the worst case power analysis if for worst voltage and temperature and best process (I will post the results for all corners analysis as soon as I organize them).

    Regards,
    Cristiano L. Santos


    Originally posted in cdnusers.org by clsantos
    • Post Points: 0
  • Fri, Oct 27 2006 8:04 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply

    I used a small block of an rfid tag of 5Kgates operating at very low frequency (640KHz) and I tested these PVT combinations:

    Case 1: WORST extraction, HIGH temperature, HIGH voltage, BEST process => 1.2637e-01 mW
    Case 2: WORST extraction, HIGH temperature, LOW voltage, BEST process => 7.8231e-02 mW
    Case 3: WORST extraction, HIGH temperature, HIGH voltage, WORST process => 1.0015e-01 mw
    Case 4: WORST extraction, HIGH temperature, LOW voltage, WORST process => 6.4237e-02 mw

    Case 5: BEST extraction, LOW temperature, LOW voltage, WORST process => 5.3186e-02 m
    Case 6: BEST extraction, LOW temperature, HIGH voltage, WORST process => 8.3718e-02 mw
    Case 7: BEST extraction, LOW temperature, LOW voltage, BEST process => 6.9326e-02 mw
    Case 8: BEST extraction, LOW temperature, HIGH voltage, BEST process => 1.1280e-01 mw

    As you have said, both voltage and process have more influence on cell delay by k_factors than by the increase of transition times. So, I will use “Case 1” as PVT point to estimate the worst IR drop.

    Thanks,
    Cristiano.


    Originally posted in cdnusers.org by clsantos
    • Post Points: 0
  • Tue, Feb 6 2007 9:20 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: PVT corner for worst case power analysis Reply


    If you really want to find the worst power. You can probably measure it on 2 cycles with a VCD from an ATPG at speed test. This will try to toggle as many FFs as possible in your designs, ignoring protocols and everything else. Then take case 1 above and you probably have yourself in your worst case scenario. Actually you can probably make it even worst by using an overdrive voltage of the type that might be used to age the part during characterization. Then of course you have the question of what do I do with that? my guess is nothing as if you design to support that you will most likely explode your design constraints. (which is why a lot of people are working on different approach to reduce test power requirement without killing test time)

    Of course I agree with Chrys's statement which I believe give an accurate view of what is being done today with the exception of analyzing thing such as leakage power in stand by mode which may not be as important for your design but is crucial for some application (battery life anyone?).

    In my personal opinion the critical items of today's design regarding power are:

    1. Simulations providing realistic use case scenario. (note that 1 is not enough especially for SOC as various area of the design might be active at different time)
    2. Accurate IR drop backannotation and usage in STA/Power analysis tools (requires accurate modeling)
    3. Accurate glitch analysis.
    4. Signal EM analysis
    5. Good decap requirement prediction (in order to help with peak power requirement without killing leakage)
    6. Education of the whole management/Customer chain i.e. There is not a single power number for a chip it all depends on use scenario.

    Now I would love to hear about what you guys are doing for each of the problems above and also if anybody as looked at SSTA like approach to power analysis i.e. the chip is not in case 1 or case 2 above but in a combination of the various parameters.

    Thanks,
    Eric.


    Originally posted in cdnusers.org by evenditti
    • Post Points: 0
Page 1 of 1 (7 items)
Sort Posts:
Started by archive at 18 Oct 2006 07:37 AM. Topic has 6 replies.