Home > Community > Forums > Digital Implementation > Designing for low-power

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Designing for low-power 

Last post Wed, Jul 11 2007 5:31 PM by archive. 2 replies.
Started by archive 12 Oct 2006 09:56 AM. Topic has 2 replies and 1152 views
Page 1 of 1 (3 items)
Sort Posts:
  • Thu, Oct 12 2006 9:56 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Designing for low-power Reply
    Hi All,

    Well, it's a bit quiet in here, so I'll post and see if I can stimulate something here.

    Before I start, I’d like to say that folks shouldn’t feel restricted to just discussing Cadence tools or issues with them in here. This is a low-power forum, and I’d like to see some discussion and debate on techniques and ideas just as much as seeing posts about specific tools (ie anything goes, as long as it is roughly on-topic).

    So, designing for low-power:

    Is power a consideration?

    What do you, as a designer, do to limit static (leakage) or dynamic power?

    How does power rate in the “traditional” trade-offs of Area, Speed and Tape-out date?

    Does your management understand power is an issue to you?

    I’ll see if this gets a few replies before I give my own answers.


    Chris


    Originally posted in cdnusers.org by Chris_Byham
    • Post Points: 5
  • Mon, Mar 26 2007 10:30 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Designing for low-power Reply

    Hi,

    Yes Indeed power is a cosideration now.(<130 nm regime).
    In my project I use Clock_gating to reduce Dynamic power.
    Leakage no presription.

    If possible Can u let us know about the Power considerations with changing Technologies and their dependencies(esp 65 nm)


    Ranga


    Originally posted in cdnusers.org by ranga
    • Post Points: 0
  • Wed, Jul 11 2007 5:31 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Designing for low-power Reply

    Ranga,

    As you move to 65 nm technology, you will see a huge increase in leakage power. Power shut off (PSO) is emerging as a common method for controlling leakage power. You simply turn off the blocks that are not being used so they don't dissipate leakage power. For example, if you are listening to music on a video iPod, the video processing circuits are not used and can be turned off to reduce leakage power.

    Supply voltage is another thing to consider. Both dynamic and leakage power are directly proportional to voltage. Many designs are using Multiple Supply Voltage (MSV). For lower performance blocks, you can use a lower supply voltage for power reduction. For higher performance blocks, you can use a higher supply voltage for performance improvement.

    Some really advanced designs use Dynamic Voltage, Frequency Scaling (DVFS). Here, you dynamically adjust the supply voltage to match the performance required. When you need high performance, you can crank up the voltage to speed up the circuits. When you don't need high performance, you can drop the voltage to save power.

    While these design techniques reduce power dissipation, they come at a cost of increased design complexity. The Common Power Format (CPF) and Cadence's low-power solution have been designed to manage this design complexity (and risk). Please visit http://www.cadence.com/lowpower/ for more details.

    Luke


    Originally posted in cdnusers.org by lukelang
    • Post Points: 0
Page 1 of 1 (3 items)
Sort Posts:
Started by archive at 12 Oct 2006 09:56 AM. Topic has 2 replies.