Hi Crispy Duck,Originally posted in cdnusers.org by EngHan
Some simple starters. See how many people make these mistakes:
1. Spare gate inputs should be tie to high or low to reduce leakage
2. decap cell has leakage; filler cell don't
3. a FF with async-set and Q/Q- can have 0.001nW less leakage than a FF
without async set/reset and Q output only. However the former is 30%
bigger in area, and don't need tie cell. If you ask the synthesis tool
to optimise leakage, which FF do you think the tool will use?