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 Designing for low power 

Last post Mon, Feb 6 2006 7:06 AM by archive. 2 replies.
Started by archive 06 Feb 2006 07:06 AM. Topic has 2 replies and 1304 views
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  • Mon, Feb 6 2006 7:06 AM

    • archive
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    Designing for low power Reply

    OK, since it's an area I have a bit of interest in, how about a couple of general questions to kick things off:

    How many people in here are actually designing for "low power"?

    What techniques are you using?

    CD


    Originally posted in cdnusers.org by crispy_duck
    • Post Points: 0
  • Tue, Apr 11 2006 8:13 AM

    • archive
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    RE: Designing for low power Reply

    Hi Crispy Duck,

    Some simple starters. See how many people make these mistakes:

    1. Spare gate inputs should be tie to high or low to reduce leakage
    2. decap cell has leakage; filler cell don't
    3. a FF with async-set and Q/Q- can have 0.001nW less leakage than a FF without async set/reset and Q output only. However the former is 30% bigger in area, and don't need tie cell. If you ask the synthesis tool to optimise leakage, which FF do you think the tool will use?

    Regards,
    Eng Han


    Originally posted in cdnusers.org by EngHan
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  • Tue, Apr 11 2006 2:16 PM

    • archive
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    RE: Designing for low power Reply

    My personal favourites:

    1) Failing to clamp outputs from a powered-domain into an unpowered one when the library has diode-protection to Vdd in all cells (Oh look, we're powering the core via a single wire!)
    2) Rebuffering feed-through nets inside a chiplet which has all its power turned-off (Oh, where has our interrupt gone???)
    3)Passing a clock from one domain to another and back, then discovering that the timing alters with respect to a path that is kept in the first domain (Why does our chip fail when we alter the voltages??)

    I could go on, but I'd like to retain the illusion that I'm competent at this sort of stuff ;-)

    CD


    Originally posted in cdnusers.org by crispy_duck
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Started by archive at 06 Feb 2006 07:06 AM. Topic has 2 replies.