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 "block based" sparse memory 

Last post Wed, Jul 11 2007 11:29 PM by archive. 1 replies.
Started by archive 14 Feb 2007 02:46 PM. Topic has 1 replies and 2187 views
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  • Wed, Feb 14 2007 2:46 PM

    • archive
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    "block based" sparse memory Reply

    This is another sparse memory model with an interface similar to shr_ram.  It attempts to improve performance by reaching a compromise between a flat implementation (used for fully/mostly implemented memories) and a keyed list implementation (used for very sparsely implemented memories) by using dynamically sized blocks to represent implemented regions.  See the user guide and examples for details.


    Originally posted in cdnusers.org by spadix
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  • Wed, Jul 11 2007 11:29 PM

    • archive
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    RE: "block based" sparse memory Reply

    Is there something similar available in System Verilog also.
    If yes, could you pprovide a example

    Regards,
    Parag


    Originally posted in cdnusers.org by parag123
    • Post Points: 0
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Started by archive at 14 Feb 2007 02:46 PM. Topic has 1 replies.