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Mixed-Signal Design Forum

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Sticky Welcome to the Cadence Mixed-Signal Forum!
started by admin  on 09 Nov 2012 10:26 AM   
0 8327 By admin
09 Nov 2012 10:26 AM   
Post invoke modelwriter
started by gnaw  on 08 Apr 2014 09:55 AM   
2 119 By gnaw
10 Apr 2014 08:10 AM   
Post Spice
started by sonnet28  on 06 Mar 2014 08:02 AM   
1 573 By Andrew Beckett
09 Apr 2014 11:50 PM   
Post cadence running slow in ubuntu
started by Darshak  on 04 Apr 2014 04:55 AM   
1 407 By Andrew Beckett
07 Apr 2014 05:57 AM   
Post How to setup Cadence ADE to simulate basic digital blocks successfully
started by bhl3302  on 19 Aug 2013 12:42 PM   
8 3623 By marten
27 Mar 2014 03:54 AM   
Post Differential Non Linearity and Integral Non Linearity for ADCs
started by analogy  on 15 Mar 2014 02:14 PM   
5 267 By smlogan
24 Mar 2014 12:29 PM   
Post Mixed-signal LVS netlist from schematic
started by bdjones1  on 16 Mar 2014 08:50 AM   
1 137 By Andrew Beckett
18 Mar 2014 03:37 PM   
Post ERROR (VACOMP-1008): Cannot compile ahdlcmi module library
started by jsaenznoval  on 14 Mar 2014 12:11 PM   
2 331 By jsaenznoval
17 Mar 2014 08:04 AM   
Post how to connect signal to a real_vector
started by sebgimi  on 04 Mar 2014 06:08 AM   
5 600 By Andrew Beckett
05 Mar 2014 01:04 AM   
Post mixed Signal simulation using Analog schematic and VHDL behaviour code
started by wrensh  on 04 Mar 2014 06:43 AM   
0 560 By wrensh
04 Mar 2014 06:43 AM   
Post VerilogA in AMS simulation: string parameter is not properly recognized
started by jsaenznoval  on 17 Feb 2014 10:19 AM   
2 1637 By jsaenznoval
21 Feb 2014 08:28 AM   
Post Vhdl-ams beginner
started by sebgimi  on 11 Feb 2014 01:15 AM   
1 1783 By Andrew Beckett
17 Feb 2014 06:10 AM   
Post How to use a Hspice model in spectre?
started by Enycin  on 15 Feb 2014 04:08 PM   
2 1840 By Enycin
16 Feb 2014 07:31 AM   
Post Using a Design Variable in an input.scs File
started by Cachi  on 13 Aug 2013 10:05 AM   
3 3853 By Andrew Beckett
14 Feb 2014 05:58 AM   
Post Switched Cap based System Noise Analysis
started by Abhishek D  on 08 Feb 2014 02:14 PM   
7 2243 By Andrew Beckett
10 Feb 2014 09:44 PM   
Post AMS simulation using ADE. How to save internal verilog module signals.
started by weebey  on 04 Feb 2014 11:56 AM   
0 2473 By weebey
04 Feb 2014 11:56 AM   
Post Which simulator is best to use for Mixed-Signal Simulation?
started by Kabal  on 23 Jan 2014 03:04 PM   
3 3405 By Andrew Beckett
27 Jan 2014 05:45 AM   
Post Defining a string parameter in a systemverilog model as a design variable
started by Soner  on 21 Aug 2013 05:29 PM   
2 7018 By Soner
24 Jan 2014 04:49 PM   
Post Custom DC Operating Point Definitions or Overwriting the .dcOpInfo.info file?
started by CadenceUser3  on 17 Jan 2014 04:55 PM   
2 3807 By CadenceUser3
21 Jan 2014 07:17 PM   
Post AMS simulation with VCD input file
started by Abhishek D  on 15 Jan 2014 11:39 AM   
3 4125 By Andrew Beckett
16 Jan 2014 02:47 AM   

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