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Custom IC Design Forum

Page 9 of 156     First ... 5678910111213 ... Last
  Topics   Replies     Views     Last Post  
Post Is the device capacitance bias-dependent or independent?
started by Alex Liao  on 05 May 2014 04:23 PM   
6 341 By Alex Liao
07 May 2014 04:37 PM   
Post monte-carlo simulation running one seed
started by frogconsultant  on 09 May 2012 01:35 AM   
12 3776 By Frank Wiedmann
07 May 2014 05:13 AM   
Post HELP!!! insert gpdk180 into IC615
started by hTmTech  on 27 Apr 2014 07:25 AM   
7 339 By hTmTech
07 May 2014 02:34 AM   
Post ADE XL - Message 1612
started by shayM  on 06 May 2014 03:28 AM   
2 194 By shayM
06 May 2014 04:12 AM   
Post Creating a user defined Voltage source
started by Debajit B  on 01 May 2014 10:39 PM   
3 231 By Debajit B
06 May 2014 12:11 AM   
Post Monte Carlo Simulation Failure
started by Jordan Morris  on 29 Apr 2014 02:51 AM   
1 205 By Jordan Morris
05 May 2014 04:22 AM   
Post ocnxlRun never returns as some splits are hung forever
started by Tajinder  on 29 Apr 2014 04:18 PM   
3 197 By Tajinder
02 May 2014 11:25 AM   
Post SpiceIn - how to map to a total width from w and m in the CDL
started by WMACH  on 01 May 2014 10:31 AM   
4 231 By skillUser
02 May 2014 08:37 AM   
Post " *Error* plus: can't handle (nil + nil) " during netlisting in icfb
started by yayla  on 15 Feb 2012 08:54 AM   
7 3081 By shila sh
02 May 2014 08:33 AM   
Post Problem in grid resolution.
started by Debajit B  on 04 Sep 2013 02:30 AM   
3 515 By Debajit B
01 May 2014 10:55 PM   
Post AMS simulation taking very small step sizes. Help in finding offending connect modules?
started by Amblikai  on 01 May 2014 07:06 AM   
0 195 By Amblikai
01 May 2014 07:06 AM   
Post Issue with DRC - "run is invalid"
started by apaj  on 30 Apr 2014 02:06 PM   
10 331 By Quek
01 May 2014 02:34 AM   
Post Extracting generic devices with Assura
started by PietroUser  on 29 Apr 2014 07:54 AM   
3 185 By Andrew Beckett
30 Apr 2014 05:28 AM   
Post Abstract Generator : abstract view with just "M1 net layer" => instead of "M1 drawing" and "M1 pin layers"
started by samung  on 29 Apr 2014 05:57 AM   
2 177 By samung
29 Apr 2014 08:02 AM   
Post Assura Layout extract.rul debug
started by PietroUser  on 10 Apr 2014 01:04 AM   
2 168 By PietroUser
29 Apr 2014 07:35 AM   
Post Modifying an extracted view for post layout simulation.
started by ghrshomali  on 20 Feb 2012 08:31 PM   
10 3735 By Mazmaz
29 Apr 2014 07:27 AM   
Post Is there a function in verilogA like "break" in C or C++ ?
started by UUinfini  on 29 Apr 2014 04:01 AM   
1 159 By Andrew Beckett
29 Apr 2014 06:14 AM   
Post Abstract Generator : tech file and origin in LEF file
started by samung  on 29 Apr 2014 03:19 AM   
2 228 By samung
29 Apr 2014 03:39 AM   
Post VerilogA definitions from ADE-XL
started by daasboe  on 29 Apr 2014 03:30 AM   
0 177 By daasboe
29 Apr 2014 03:30 AM   
Post Pin definition in layout.oa (layer, connectivity) ?
started by samung  on 28 Apr 2014 08:56 AM   
2 186 By samung
29 Apr 2014 02:19 AM   

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