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Custom IC Design Forum

Page 8 of 159     First ... 456789101112 ... Last
  Topics   Replies     Views     Last Post  
Post Modeling and simulation of FinFET in cadence
started by RAJ JOHRI  on 09 Aug 2012 06:37 AM   
11 2592 By Chen23
27 Jun 2014 10:46 AM   
Post Labels are created in VLE while doing streaming in a GDS file.
started by RFStuff  on 27 Jun 2014 08:06 AM   
1 751 By Andrew Beckett
27 Jun 2014 10:16 AM   
Post Problem Photodiode modelling in Verilog-A
started by papy07  on 26 Jun 2014 03:03 PM   
4 814 By Andrew Beckett
27 Jun 2014 06:37 AM   
Post Results Browser in IC5.10.41
started by ag2888  on 25 Jun 2014 12:57 AM   
5 827 By Andrew Beckett
27 Jun 2014 05:46 AM   
Post Different simulation results for local and distributed host mode
started by ag2888  on 25 Jun 2014 02:08 AM   
1 784 By Andrew Beckett
27 Jun 2014 05:44 AM   
Post LVS caliber error
started by Bahaa  on 25 Jun 2014 10:06 AM   
2 776 By Bahaa
25 Jun 2014 02:21 PM   
Post Ocean/Calculator expressions and their units
started by MicheleA  on 14 Aug 2012 05:47 AM   
12 4002 By XinjiePI
25 Jun 2014 01:50 PM   
Post ADExl problem with bus notation
started by sram8t  on 16 Jun 2014 07:41 AM   
3 1137 By sram8t
25 Jun 2014 06:27 AM   
Post How to creat the "layout" version for a new device
started by UUinfini  on 23 Jun 2014 07:54 AM   
2 861 By UUinfini
23 Jun 2014 08:49 AM   
Post Transient Noise Analysis to Calculate PLL Phase Noise
started by F1111  on 20 Jun 2014 03:04 PM   
0 987 By F1111
20 Jun 2014 03:04 PM   
Post Cadence Virtuoso 6.16 model cards
started by DigitalOsama  on 19 Jun 2014 01:23 PM   
3 991 By Andrew Beckett
20 Jun 2014 09:36 AM   
Post Custom deep trench capacitor
started by madhanmo  on 19 Jun 2014 12:42 AM   
3 1013 By Andrew Beckett
20 Jun 2014 01:29 AM   
Post component property display in schematic editor
started by apple419  on 17 Jun 2014 07:48 PM   
3 1051 By apple419
18 Jun 2014 09:38 AM   
Post risetime and falltime in the calculator
started by surreyian  on 27 Jul 2012 05:24 AM   
4 5116 By HassanSyed
18 Jun 2014 07:14 AM   
Post DIVA LVS global error: Cannot find switch master cell for instance R1 in cellView (mimcap schematic) from viewlist 'lvs...
started by Alex Liao  on 17 Jun 2014 04:25 PM   
0 1046 By Alex Liao
17 Jun 2014 04:25 PM   
Post Mathematical explanation for resistor mismatch parameters
started by cadwiz  on 10 Jun 2014 11:51 AM   
1 1496 By Andrew Beckett
17 Jun 2014 03:11 AM   
Post Encryption netlist compatibility
started by Kovinko  on 10 Jun 2014 02:29 AM   
4 1614 By Andrew Beckett
17 Jun 2014 02:49 AM   
Post very long bit pattern for vbit source
started by Zitty  on 30 Oct 2012 02:44 PM   
12 4452 By Andrew Beckett
17 Jun 2014 01:27 AM   
Post Sweeping component parameters for many components in ADE GXL
started by Kabal  on 15 Jun 2014 07:06 PM   
0 1137 By Kabal
15 Jun 2014 07:06 PM   
Post Monte Carlo over swept oppoints
started by neuroAnalog  on 13 Jun 2014 06:38 PM   
0 1261 By neuroAnalog
13 Jun 2014 06:38 PM   

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