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Custom IC Design Forum

Page 4 of 155     First 12345678 ... Last
  Topics   Replies     Views     Last Post  
Post component property display in schematic editor
started by apple419  on 17 Jun 2014 07:48 PM   
3 734 By apple419
18 Jun 2014 09:38 AM   
Post risetime and falltime in the calculator
started by surreyian  on 27 Jul 2012 05:24 AM   
4 4748 By HassanSyed
18 Jun 2014 07:14 AM   
Post DIVA LVS global error: Cannot find switch master cell for instance R1 in cellView (mimcap schematic) from viewlist 'lvs...
started by Alex Liao  on 17 Jun 2014 04:25 PM   
0 711 By Alex Liao
17 Jun 2014 04:25 PM   
Post Mathematical explanation for resistor mismatch parameters
started by cadwiz  on 10 Jun 2014 11:51 AM   
1 1147 By Andrew Beckett
17 Jun 2014 03:11 AM   
Post Encryption netlist compatibility
started by Kovinko  on 10 Jun 2014 02:29 AM   
4 1254 By Andrew Beckett
17 Jun 2014 02:49 AM   
Post very long bit pattern for vbit source
started by Zitty  on 30 Oct 2012 02:44 PM   
12 3970 By Andrew Beckett
17 Jun 2014 01:27 AM   
Post Sweeping component parameters for many components in ADE GXL
started by Kabal  on 15 Jun 2014 07:06 PM   
0 816 By Kabal
15 Jun 2014 07:06 PM   
Post Monte Carlo over swept oppoints
started by neuroAnalog  on 13 Jun 2014 06:38 PM   
0 931 By neuroAnalog
13 Jun 2014 06:38 PM   
Post Plotting Gm vs Vgs for different values of Vbs
started by wgtkan  on 11 Jun 2014 11:33 AM   
2 1097 By wgtkan
11 Jun 2014 04:54 PM   
Post Problem in reading-in in Spectre
started by SaeedR  on 27 May 2014 04:21 PM   
5 1535 By Andrew Beckett
11 Jun 2014 02:46 PM   
Post Grid spacing for 45nm GPDK process
started by madhanmo  on 11 Jun 2014 06:59 AM   
0 1073 By madhanmo
11 Jun 2014 06:59 AM   
Post How to eliminate unused empty cells when importing GDS
started by marklin  on 10 Jun 2014 08:21 AM   
0 1131 By marklin
10 Jun 2014 08:21 AM   
Post Error while importing .gds in cadence IC 6.16
started by radiowaves  on 07 Jun 2014 09:48 PM   
4 1357 By Andrew Beckett
10 Jun 2014 08:00 AM   
Post pipo.log and strmOut.log
started by radiowaves  on 09 Jun 2014 11:33 AM   
2 1154 By radiowaves
09 Jun 2014 01:25 PM   
Post XL Layout issue with custom Library layout sourcing the Schematic.
started by JP Layout  on 06 Jun 2014 02:47 PM   
0 1460 By JP Layout
06 Jun 2014 02:47 PM   
Post NC-Verilog simulation error
started by ahmed osama  on 06 Jun 2014 04:22 AM   
0 1417 By ahmed osama
06 Jun 2014 04:22 AM   
Post freeze with virtuoso layout
started by Fabb  on 06 Jun 2014 12:43 AM   
1 1486 By Andrew Beckett
06 Jun 2014 01:20 AM   
Post do stb analysis on five stage invter ring osc
started by xianweng  on 04 Jun 2014 07:37 AM   
3 1439 By xianweng
05 Jun 2014 07:17 AM   
Post Unable to run Monte Carlo ADEXL-1723
started by Faizalism  on 05 Jun 2014 12:37 AM   
3 1402 By Andrew Beckett
05 Jun 2014 02:24 AM   
Post How to do a parametric analysis for a model parameter ?
started by Ahmed Taha  on 30 May 2014 04:38 AM   
2 1477 By smlogan
04 Jun 2014 08:21 AM   

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