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Custom IC Design Forum

Page 3 of 155     First 1234567 ... Last
  Topics   Replies     Views     Last Post  
Post Vbit Source
started by DigitalOsama  on 28 Jun 2014 10:30 AM   
3 409 By Andrew Beckett
30 Jun 2014 12:16 PM   
Post ADE Cadence IC 6.1.5 Reliability Simulation
started by DigitalOsama  on 29 Jun 2014 04:40 AM   
1 388 By Andrew Beckett
30 Jun 2014 06:42 AM   
Post How to run ADEXL without re-netlisting?
started by dboy1394  on 22 Feb 2014 03:52 PM   
2 2061 By pthoppay
27 Jun 2014 03:01 PM   
Post Modeling and simulation of FinFET in cadence
started by RAJ JOHRI  on 09 Aug 2012 06:37 AM   
11 2237 By Chen23
27 Jun 2014 10:46 AM   
Post Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)
started by RFStuff  on 27 Jun 2014 10:28 AM   
0 434 By RFStuff
27 Jun 2014 10:28 AM   
Post Labels are created in VLE while doing streaming in a GDS file.
started by RFStuff  on 27 Jun 2014 08:06 AM   
1 446 By Andrew Beckett
27 Jun 2014 10:16 AM   
Post Problem Photodiode modelling in Verilog-A
started by papy07  on 26 Jun 2014 03:03 PM   
4 500 By Andrew Beckett
27 Jun 2014 06:37 AM   
Post Results Browser in IC5.10.41
started by ag2888  on 25 Jun 2014 12:57 AM   
5 524 By Andrew Beckett
27 Jun 2014 05:46 AM   
Post Different simulation results for local and distributed host mode
started by ag2888  on 25 Jun 2014 02:08 AM   
1 473 By Andrew Beckett
27 Jun 2014 05:44 AM   
Post Markingnet throught tilenot layers
started by bharath2k4  on 26 Jun 2014 02:02 AM   
0 448 By bharath2k4
26 Jun 2014 02:02 AM   
Post virtuoso possible outputs in IC610
started by jagdev  on 25 Jun 2014 08:00 PM   
0 468 By jagdev
25 Jun 2014 08:00 PM   
Post LVS caliber error
started by Bahaa  on 25 Jun 2014 10:06 AM   
2 475 By Bahaa
25 Jun 2014 02:21 PM   
Post Ocean/Calculator expressions and their units
started by MicheleA  on 14 Aug 2012 05:47 AM   
12 3591 By XinjiePI
25 Jun 2014 01:50 PM   
Post ADExl problem with bus notation
started by sram8t  on 16 Jun 2014 07:41 AM   
3 810 By sram8t
25 Jun 2014 06:27 AM   
Post ncprotect when using user-defined keys
started by James Bailey  on 24 Jun 2014 08:46 AM   
0 522 By James Bailey
24 Jun 2014 08:46 AM   
Post how to use ADE_L to plot waveform after command line simulation
started by xianweng  on 21 Jun 2014 12:07 AM   
6 703 By xianweng
24 Jun 2014 05:43 AM   
Post How to creat the "layout" version for a new device
started by UUinfini  on 23 Jun 2014 07:54 AM   
2 559 By UUinfini
23 Jun 2014 08:49 AM   
Post Transient Noise Analysis to Calculate PLL Phase Noise
started by F1111  on 20 Jun 2014 03:04 PM   
0 665 By F1111
20 Jun 2014 03:04 PM   
Post Cadence Virtuoso 6.16 model cards
started by DigitalOsama  on 19 Jun 2014 01:23 PM   
3 676 By Andrew Beckett
20 Jun 2014 09:36 AM   
Post Custom deep trench capacitor
started by madhanmo  on 19 Jun 2014 12:42 AM   
3 699 By Andrew Beckett
20 Jun 2014 01:29 AM   

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